DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 106

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.5 Gapped Clocks
The transmit and receive output clocks can be gapped in certain configurations. See
for the configuration settings. The gapped clocks are active during DS3 or E3 framed payload bits or DS3 or E3
fractional overhead bits depending on which mode the device is configured for.
In the internal DS3 or E3 fractional modes, the transmit gapped clock is created by the logical OR of the TCLKOn
and TFOHENOn signals creating a positive or negative clock edge for each fractional overhead bit, the receive
gapped clock is created by the logical OR of the RCLKOn and RFOHENOn signals. In the internal DS3 or E3 non-
fractional modes, the transmit gapped clock is created by the logical OR of the TCLKOn and TDENn signals
creating a positive or negative clock edge for each payload bit, the receive gapped clock is created by the logical
OR of the RCLKOn and RDENn signals.
When the output clock is disabled, the gapped output signal is high during clock periods if the pin is not inverted;
otherwise it will be low.
The gapped clocks are very useful when the data being clocked does not need to be aligned with any frame
structure. The data is simply clocked one bit at a time as a continuous data stream.
Figure 10-4. Example IO Pin Clock Muxing
TSER
TCLKI
RLCLK
CLAD CLOCKS
STS-1 CLK
RX LIU CLK
DS3 CLK
E3 CLK
PIN INVERT
PIN INVERT
PIN INVERT
DELAY
TFTS
0
1
CLOCK TREE
CLOCK TREE
CLOCK TREE
INTERNAL
INTERNAL
INTERNAL
SIGNAL
SIGNAL
SIGNAL
D
SET
CLR
Q
Q
106
D
D
D
D
SET
CLR
SET
CLR
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
Q
Q
INTERNAL
DELAY
SIGNAL
DELAY
DELAY
TFTS
TLTS
RFTS
0
1
0
1
0
1
D
D
D
SET
CLR
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
Table 10-24
RCLKO
TCLKO
TLCLK
TDEN
RSER
TPOS
and
Table 10-31