DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 240

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 2: Transmit Driver Monitor Status (TDM) This bits indicates the status of the transmit monitor circuit in the
transmit LIU.
Bit 1: Receive Loss Of Lock Status (RLOL) This bits indicates the status of the receive LIU clock recovery PLL
circuit.
Bit 0: Performance Monitoring Update Status (PMS) This bits indicates the status of all active performance
monitoring register and counter update signals in this port. It is an “AND” of all update status bits and is not set until
all performance registers are updated and the counters reset. In software update modes, the update request bit
PORT.CR1.PMU should be held high until this status bit goes high.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 7: Receive Line Clock Activity Status Latched (RLCLKA) This bit will be set when the signal on the RLCLKn
pin or the recovered clock from the LIU for this port is active.
Bit 6: Transmit Input Clock Activity Status Latched (TCLKIA) This bit will be set when the signal on the TCLKIn
pin for this port is active.
Bit 2: Transmit Driver Monitor Status Latched (TDML) This bit will be set when the PORT.SR.TDM status bit
changes from low to high. This bit will also set the PORT.ISR.PSR status bit if the PORT.SRIE.TDMIE bit is
enabled. The interrupt pin will be driven when this bit is set, the PORT.SRIE.TDMIE bit is set, and the
corresponding GL.ISRIE.PISRIE[4:1] bit is also set.
Bit 1: Receive Loss Of Lock Status Latched (RLOLL) This bit will be set when the PORT.SR.RLOL status bit
changes from low to high. This bit will also set the PORT.ISR.PSR status bit if the PORT.SRIE.RLOLIE bit is
enabled. The interrupt pin will be driven when this bit is set, the PORT.SRIE.RLOLIE bit is set, and the
corresponding GL.ISRIE.PISRIE[4:1] bit is also set.
Bit 0: Performance Monitoring Update Status Latched (PMSL) This bit will be set when the PORT.SR.PMS
status bit changes from low to high. This bit will also set the PORT.ISR.PSR status bit if the PORT.SRIE.PMUIE bit
is enabled. The interrupt pin will be driven when this bit is set, the PORT.SRIE.PMUIE bit is set, and the
PORT.SRIE.PMSIE bit are set.
0 = Transmit output not over loaded
1 = Transmit signal is overloaded
1 = Not locked to the incoming signal
0 = The associated update request signal is low
1 = The requested performance register updates are all completed
0 = Locked to the incoming signal
RLCLKA
15
15
—
—
—
7
7
TCLKIA
14
14
—
—
—
6
6
PORT.SR
Port Status Register
(0,2,4,6)52h
PORT.SRL
Port Status Register Latched
(0,2,4,6)54h
13
13
—
—
—
—
5
5
12
12
—
—
—
—
4
4
240
11
11
—
—
—
—
3
3
TDML
TDM
10
10
—
—
2
2
RLOLL
RLOL
—
—
9
1
9
1
PMSL
PMS
—
—
8
0
8
0