DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 352

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DS3181

Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3181

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3181+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3181N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Bit 1: Receive Header Pattern Cell Count Interrupt Enable (RHPCIE) – This bit enables an interrupt if the
RHFCL bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Receive Corrected Header Cell Count Interrupt Enable (RCHCIE) – This bit enables an interrupt if the
RCHCL bit in the CP.RSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Cell Count (RCC[15:0]) – Lower 16 bits of 24 bits. Register description follows next register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Receive Cell Count (RCC[23:16]) - Upper 8 bits of Register.
Receive Cell Count (RCC[23:0]) – These 24 bits indicate the number of cells stored in the receive FIFO. Note:
Cells discarded due to system loopback or an overflow condition will be included in this count. This register is
updated via the PMU signal (see Section 10.4.5).
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
RCC15
RCC23
RCC7
15
15
0
7
0
0
7
0
RCC14
RCC22
RCC6
14
14
0
6
0
0
6
0
CP.RCCR1
Cell Processor Receive Cell Count Register 1
(1,3,5,7)D4h
CP.RCCR2
Cell Processor Receive Cell Count Register 2
(1,3,5,7)D6h
RCC13
RCC21
RCC5
13
13
0
5
0
0
5
0
RCC12
RCC20
RCC4
12
12
0
0
0
0
4
4
352
RCC11
RCC19
RCC3
11
11
0
3
0
0
3
0
RCC10
RCC18
RCC2
10
10
0
2
0
0
2
0
RCC17
RCC9
RCC1
9
0
1
0
9
0
1
0
RCC16
RCC8
RCC0
8
0
0
0
8
0
0
0

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