DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 69

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.1.4
The RDATn pin is available when the line interface is in the UNI mode. The ROHMIn pin is available when the
framer is in one of the “-OHM” modes. The RLCVn pin is available when the line interface is in the UNI mode and
the framer is not in one of the “-OHM” modes. The line interface is forced into the UNI mode when the framer is in
one of the “-OHM” modes.
The ROHMIn pin is used to mark the RDATn bits that will be ignored by the internal receive logic. When the
ROHMIn pin is high, the internal framers and data sinks will ignore the corresponding RDATn bits. In the “- OHM
Octet” framing modes, the data on RDATn is octet aligned with the ROHMIn signal, the first bit of the serial data on
RDATn is the MSB (Bit 1) of a payload Octet.
All bits on the RDATn pin, even the bits that are marked by ROHMIn, will come out the RSERn pin, if the RSERn
pin is enabled.
The signal on the RLCVn pin enables the BPV counter, which is in the line interface, to increment each clock it is
high.
The RDATn, ROHMIn and RLCVn signals are sampled at the rising edge of the reference clock signal if the clock
pin is not inverted; otherwise they are sampled at the negative edge. The RLCLKn clock pin is the clock reference
used for the RDATn, ROHMIn and RLCVn signals. The RDATn, ROHMIn and RLCVn pins can be inverted. See
Figure 8-7
Figure 8-7. RX Line IO OHM UNI Functional Timing Diagram
Figure 8-8. RX Line IO UNI Octet Aligned OHM Functional Timing Diagram
8.3.2
Figure 8-9
Figure 8-9. DS3 Framing Receive Overhead Port Timing
RLCLK
RLCLK
ROHM
ROHM
RDAT
RLVC
RDAT
ROHSOF
ROHCLK
ROH
DS3/E3 Framing and PLCP Overhead Functional Timing
UNI Mode Receive Pin Functional Timing
and
shows the relationship of the DS3 receive-overhead port pins.
B6 B7 B8
Octet n
F73
Figure
1
C73
2
INC BPV COUNTER TWICE
F74
8-8.
3
X1
4
EXT OH BIT LOCATIONS
F11
5
RDAT DATA WILL BE IGNORED
C11
6
F12
7
C12
8
F13
INC BPV COUNTER ONCE
9
C13
10
F14
11
69
B1 B2 B3 B4 B5 B6 B7 B8 B1
X2
12
ATM Cell /Packet Octet n+1
F21
13
C21
14
F22
15
C22
16
F23
17
C23
18
F24
19
P1
20
F31
21
C31
22
F32
23
C32
24