DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 57

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RPOHSOFn /
TDATA[31:0]
RFOHENOn
RSOFOn /
TADR[4:0]
RDENn /
TSCLK
PIN
TYPE
O
I
I
I
Receive Framer Start Of Frame /Data Enable / PLCP Overhead Start Of Frame. See
Table 10-30.
RSOFOn: When the port framer is configured for External Fractional or Flexible
Fractional mode and the RSOFOn pin function is enabled, or when it is configured for
one of the DS3 or E3 framed only modes and the port pins are enabled and the
RSOFOn pin function is enabled, this signal is used to indicate the start of the DS3/E3
frame. This signal indicates the first DS3/E3 overhead bit on the RSERn pin when
high. The signal is updated on the positive clock edge of the referenced clock pin if
the clock pin signal is not inverted, otherwise it is updated on the falling edge of the
clock. The signal is typically referenced to the RCLKOn receive clock output pin, but it
can be referenced to the RLCLKn clock input pin.
This signal can be inverted.
RDENn: When the port framer is configured for External Fractional or Flexible
Fractional mode and the RDENn pin function is enabled and the port pins are enabled
and the RDENn pin function is enabled, this signal is used to indicate the DS3/E3
payload bit positions of the data on the RSERn pin. The signal goes high during each
DS3/E3 payload bit and goes low during each DS3/E3 overhead bit. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the RCLKOn receive clock output pin, but it can be referenced
to the RLCLKn clock input pin.
This signal can be inverted.
RPOHSOFn: When the port framer is configured for one of the PLCP framing modes
and the port pins are enabled, this signal is used to mark the start of a DS3 or E3
PLCP overhead sequence on the RPOHn pins. The sequence starts on the same
high to low transition of the RPOHCLKn clock that this signal is high. This signal is
updated at the same time as the RPOHCLKn signal transitions high to low.
This signal can be inverted.
RFOHENOn: When the port framer is configured for internal fractional mode and the
port pins are enabled, this signal is used to indicate the fractional overhead bit
positions of the data on the RSERn pin. The signal goes high during each DS3/E3
fractional overhead bit and goes low during each DS3/E3 fractional payload bit. The
signal is updated on the positive clock edge of the referenced clock pin if the clock pin
signal is not inverted, otherwise it is updated on the falling edge of the clock. The
signal is typically referenced to the RCLKOn receive clock output pin, but it can be
referenced to the RLCLKn clock input pin.
This signal can be inverted.
Transmit System Clock
TSCLK: This signal is used to sample or update the other transmit system interface
signals.
TSCLK has a maximum frequency of 66 MHz in L3 modes and 52 MHz in L2 modes.
Transmit Address [4:0]
TADR[4:0]: In UTOPIA L2, UTOPIA L3 or POS-PHY L2 modes, this 5-bit address
bus is used by the ATM/Link layer device to select a specific port for data transfer or
to poll for FIFO status..
In POS-PHY L3 modes, this 5-bit address is used by the Link layer device to poll for
FIFO status.
TADR[4] is the MSB and TADR[0] is the LSB. This bus is sampled on the rising edge
of TSCLK.
Transmit Data [31:0]
TDATA[31:0]: This 32-bit data bus is used to transfer cell/packet data from the
ATM/Link layer device. This bus is sampled on the rising edge of TSCLK.
In 32-bit mode, TDATA[31] is the MSB and TDATA[0] is the LSB.
In 16-bit mode, TDATA[15] is the MSB, TDATA[0] is the LSB, and TDATA[31:16] are
not used and ignored.
UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE
57
FUNCTION