DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 168

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AIS signal is absent, and it is reset when an AIS signal is absent for 10 to 17 consecutive DS3 frames. An AIS
condition is terminated when an AIS signal is absent for 10 to 17 consecutive DS3 frames.
A Receive Unframed All 1’s (RUA1) condition is declared if in each of 4 consecutive 2047 bit windows, five or less
zeros are detected and an OOF condition is continuously present. A RUA1 condition is terminated if in each of 4
consecutive 2047-bit windows, six or more zeros are detected or an OOF condition is continuously absent.
An Idle Signal (Idle) is a DS3 signal with valid F-bits, M-bits, and P-bits (P
to one, C
after each overhead bit. In C-bit mode, an Idle signal is present when a DS3 frame is received with valid F-bits, M-
bits, and P-bits, both X-bits set to one, C
matching the overhead aligned 1100 pattern. In M23 mode, an Idle signal is present when a DS3 frame is received
with valid F-bits, M-bits, and P-bits, both X-bits set to one, and all but seven or fewer payload data bits matching
the T3 overhead aligned 1100 pattern. An Idle signal is absent when a DS3 frame is received that does not meet
aforementioned criteria for an Idle signal being present. The Idle integration counter declares an Idle condition
when it has been active for a total of 10 to 17 DS3 frames. The Idle integration counter is active (increments count)
when an Idle signal is present, it is inactive (holds count) when an Idle signal is absent, and it is reset when an Idle
signal is absent for 10 to 17 consecutive DS3 frames. An Idle condition is terminated when an Idle signal is absent
for 10 to 17 consecutive DS3 frames.
A Remote Defect Indication (RDI) condition (also called a far-end SEF/AIS defect condition) is declared when four
consecutive DS3 frames are received with the X-bits (X
four consecutive DS3 frames are received with the X-bits set to one.
A DS3 Framing Format Mismatch (DS3FM) condition is declared when the DS3 format programmed (M23, C-bit)
does not match the incoming DS3 signal-framing format. A DS3FM condition is terminated when the incoming DS3
signal-framing format is the same format as programmed. Framing errors are determined by comparing F-bits and
M-bits to their expected values. The type of framing errors accumulated is programmable (OOF, F & M, F, or M).
An OOF error increments the count whenever OOF condition is first detected. An F & M error increments the count
once for each F-bit or M-bit that does not match its expected value (up to 31 per DS3 frame). An F error increments
the count once for each F-bit that does not match its expected value (up to 28 per DS3 frame). An M error
increments the count once for each M-bit that does not match its expected value (up to 3 per DS3 frame).
P-bit parity errors are determined by calculating the parity of the current DS3 frame (payload bits only), and
comparing the calculated parity to the P-bits (P
match P
C-bit parity errors (C-bit format only) are determined by calculating the parity of the current DS3 frame (payload bits
only), and comparing the calculated parity to the C-bits in sub-frame three (C
frame. If the calculated parity does not match C
FEBE errors (C-bit format only) are determined by the C-bits in sub-frame four (C
indicates no error and any other value indicates an error.
10.10.5 C-bit DS3 Framer/Formatter
10.10.5.1 Transmit C-bit DS3 Frame Processor
The C-bit DS3 frame format is shown in
DS3 Frame
1
31
or P
, C
32
2
, a single P-bit parity error is declared.
, and C
33
are set to zero, and the payload bits are set to a 1100 pattern starting with 11 immediately
Figure
31
, C
32
31
, and C
10-40.
1
, C
and P
32
, or C
Table 10-34
33
168
1
2
) in the next DS3 frame. If the calculated parity does not
and X
set to zero, and all but seven or fewer payload data bits
33
, a single C-bit parity error is declared.
2
) set to zero. An RDI condition is terminated when
shows the function of each overhead bit in the
1
and P
31
2
, C
41
). The X-bits (X
, C
32
, and C
42
, and C
33
43
) in the next DS3
). A value of 111
1
and X
2
) are set