DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 228

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 2: Transmit System Fill Level Inversion (TFLVI) – When 0, the polarity of the TPXA, TDXA, and TSPA
signals will be normal (high for data available). When 1, the polarity of the TPXA, TDXA, and TSPA signals will be
inverted (low for data available).
Bit 1: Transmit System Interface Byte Reordering Enable (TSBRE) – When 0, byte reordering is disabled, and
the first byte transmitted is transferred across the system interface as the most significant byte (TDATA[31:24] in
32-bit mode or TDATA[15:8] in 16-bit mode). When 1, byte reordering is enabled, and the first byte transmitted is
transferred across the system interface as the least significant byte (TDATA[7:0]).
Bit 0: Transmit System HEC Transfer (THECT) – When 0, The HEC byte is not transferred across the transmit
system interface. When 1, the HEC byte is transferred across the transmit system interface with the cell data.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 1: Transmit System Interface Clock Active (TSCLKAL) – This bit is set when TSCLK is active.
Bit 0: Transmit System Interface Parity Error Latched (TPREL) – This bit is set when a parity error is detected
during a data transfer on the Transmit System Interface bus.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Transmit System Interface Parity Error Interrupt Enable (TPREIE) – This bit enables an interrupt if the
TPREL bit in the TSISRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
15
15
—
—
—
—
0
7
0
7
14
14
—
—
—
—
0
6
0
6
SI.TSRL
System Interface Transmit Status Register Latched
032h
SI.TSRIE
System Interface Transmit Status Register Interrupt Enable
034h
13
13
—
—
—
—
0
5
0
5
12
12
—
—
—
—
0
0
4
4
228
11
—
—
11
—
—
3
0
3
0
10
—
—
2
10
—
—
0
2
0
TSCLKAL
—
9
1
—
—
9
0
1
0
TPREL
TPREIE
—
8
0
—
8
0
0
0