DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 105

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-9. Receive Framer Pin Signal Timing Source Select
10.2.4 Clock Structures On Signal IO Pins
The signals on the input pins (RFOHENIn, TOHMIn/TSOFIn, TFOHn/TSERn, TFOHENIn) can be used with any of
the clock pins for setup/hold timing on clock input and output pins. There will be a flop at each input whose clock is
connected to the signal from the input or output clock source pins with as little delay as possible from the signal on
the clock IO pins. This means using the input clock signal before the delays of the internal clock tree to clock the
input signals, and using the output clock signals used to drive the output clock pins to clock the input signals.
The signals on the output pins (TPOSn/TDATn, TNEGn/TOHMOn, TSOFOn/TDENn/TFOHENOn, RSERn,
RSOFOn/RDENn/RFOHENOn) can be used with any of the clock sources for delay timing. There will be a flop at
each output whose clock is connected to the signal from the input or output clock source pins with as little delay as
possible from the signal on the clock IO pins. This means using the input clock signal before the delays of the
internal clock tree to clock the input signals, and using the output clock signals to drive the output clock pins to
clock the input signals.
LOOPT
1
1
1
0
0
0
0
0
0
0
0
0
DLB (100) or LLB&DLB(110)
DLB (100) or LLB&DLB(110)
not LLB, DLB or PLB (00X)
PLB (011) or DLB (100) or
PLB (011) or DLB (100)
not LLB&DLB(110)
not LLB&DLB(110)
not DLB (100) and
not DLB (100) and
DLB&LLB (110)
ALB (001)
LLB (010)
LBM[2:0]
XXX
XXX
XXX
LIUEN
X
X
X
X
X
X
0
1
0
1
0
1
105
CLADC
X
X
X
X
X
X
X
X
X
X
0
1
RFTS
0
1
1
0
0
0
0
0
1
1
1
1
RCLKOn, TLCLKn, TCLKOn
RLCLKn
No valid timing to any input clock
pin
RCLKOn, TLCLKn, TCLKOn
RCLKOn, TLCLKn, TCLKOn
RCLKOn, TCLKOn
RCLKOn, TLCLKn
RCLKOn
No valid timing to any input clock
pin
TCLKIn
RLCLKn
No valid timing to any input clock
pin
VALID TIMING TO THESE
CLOCK PINS