DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 388

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.5 System Interface AC Characteristics
The AC characteristics of the system interface depend upon the mode of the interface. While UTOPIA vs. POS-
PHY mode does not have an effect on the AC characteristics, L2 vs. L3 does. Therefore, there are two tables: one
for L2
Figure 18-3,
Table 18-5. System Interface L2 Timing
(V
Note 1:
Note 2:
Note 3:
RSCLK and TSCLK
RSCLK and TSCLK
RSCLK and TSCLK
RADR and REN
RADR and REN
RDATA, RPRTY, RPXA,
RSOX, REOP, RVAL,
RMOD, and RERR
RDATA, RPRTY, RPXA,
RSOX, REOP, RVAL,
RMOD, and RERR
RDATA, RPRTY, RPXA,
RSOX, REOP, RVAL,
RMOD, and RERR
TDATA, TPRTY, TADR,
TEN, TSOX, TEOP,
TMOD, and TERR
TDATA, TPRTY, TADR,
TEN, TSOX, TEOP,
TMOD, and TERR
TPXA and TSPA
TPXA and TSPA
TPXA and TSPA
DD
SIGNAL NAME(S)
= 3.3V ±5%, T
(Table
The input/output timing reference level for all signals is V
Rise and fall times are measured at output side with the output unloaded. Rise time is measured from 20% to 80% V
is measured from 80% to 20% V
These times are met with a 30pF, 300 Ω load on the associated output pin.
and
18-5) and one for L3
Figure 18-6
j
= -40°C to +125°C.)
SYMBOL
apply to this
t2/t1
f1
t3
t5
t6
t7
t8
t9
t5
t6
t7
t8
t9
(Table
OH
.
interface.
Clock frequency (1/t1) (Note 1)
Clock duty cycle (Note 1)
Rise/fall times (Notes 1, 2)
Hold time from RSCLK (Note 1)
Setup time to RSCLK (Note 1)
Delay from RSCLK (Notes 1, 3)
From high-Z delay from RSCLK
(Notes 1, 3)
To high-Z delay from RSCLK
(Notes 1, 3)
Hold time from TSCLK (Note 1)
Setup time to TSCLK (Note 1)
Delay from TSCLK (Notes 1, 3)
From high-Z delay from TSCLK
(Notes 1, 3)
To high-Z delay from TSCLK
(Notes 1, 3)
18-6). The generic timing definitions shown in
DESCRIPTION
388
DD
/2.
MIN
3.5
3.5
40
0
0
2
2
2
0
2
2
2
Figure
TYP
50
18-1,
MAX
60
52
12
12
15
12
12
15
2
Figure 18-2,
OH
. Fall time
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%