DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 231

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4 Per-Port Common
12.4.1 Per-Port Common Register Map
Table 12-23. Per-Port Common Register Map
12.4.2 Per-Port Common Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Nibble Align Disable (NAD). This bit is used to disable the nibble alignment of the transmit ATM cells in
direct mapped DS3 or E3 G.832 framing modes. It must be set when in DS3 M23 mode and the C-bits are used for
ATM payload.
Bits 14 to 12: Payload AIS Select [2:0] (PAIS[2:0]). This bit controls when an unframed all ones signal is forced
on the receive data path after the receive framer and payload loopback mux. Default: Payload AIS always sent.
See
Bits 11 to 10: Line AIS Select [1:0] (LAIS[1:0). These bits control when a DS3 framed AIS or an unframed all
ones signal is to be transmitted on TPOSn/TNEGn and/or TXPn/TXNn. The signal on TPOSn/TNEGn can be AMI
or unipolar. This signal is sent even when in diagnostic loopback and always over-rides signals from the framers.
Default: AIS sent if DLB is enabled. See
Bit 9: BERT Enable (BENA). This bit is used to enable the BERT logic. The BERT pattern will be the payload data
replacing the cell or packet data from the system interface.
(0,2,4,6)4Ah
(0,2,4,6)4Ch
(0,2,4,6)4Eh
(0,2,4,6)5Ah
(0,2,4,6)5Ch
(0,2,4,6)5Eh
(0,2,4,6)40h
(0,2,4,6)42h
(0,2,4,6)44h
(0,2,4,6)46h
(0,2,4,6)48h
(0,2,4,6)50h
(0,2,4,6)52h
(0,2,4,6)54h
(0,2,4,6)56h
(0,2,4,6)58h
ADDRESS
Table
0 = Nibble alignment enabled
1 = Nibble alignment disabled
0 = BERT logic disabled and powered down
1 = BERT logic enabled
10-19.
TMEI
NAD
15
0
7
0
PORT.SRIE
PORT.INV1
REGISTER
PORT.CR1
PORT.CR2
PORT.CR3
PORT.CR4
PORTINV2
PORT.SRL
PORT.ISR
PORT.SR
—
—
—
—
—
—
PAIS2
MEIM
14
0
6
0
PORT.CR1
Port Control Register 1
(0,2,4,6)40h
Port Control Register 1
Port Control Register 2
Port Control Register 3
Port Control Register 4
Port IO Invert Control Register 1
Port IO Invert Control Register 2
Unused
Port Interrupt Status Register
Port Status Register
Port Status Register Latched
Port Status Register Interrupt Enable
Unused
Unused
Unused
Unused
Unused
PAIS1
Table
13
REGISTER DESCRIPTION
—
—
0
5
10-18.
PMUM
PAIS0
12
0
0
4
231
LAIS1
PMU
11
0
3
0
LAIS0
PD
10
0
2
1
RSTDP
BENA
9
0
1
1
HDSEL
RST
8
0
0
0