DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 4

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9
10 FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
9.1
10.1 P
10.2 C
10.3 R
10.4 G
10.5 P
10.6 UTOPIA/POS-PHY/SPI-3 S
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
INITIALIZATION AND CONFIGURATION
9.1.1
9.1.2
9.1.3
10.1.1 8/16-Bit Bus Widths.............................................................................................................................. 96
10.1.2 Ready Signal (
10.1.3 Byte Swap Modes ................................................................................................................................ 96
10.1.4 Read-Write/Data Strobe Modes........................................................................................................... 96
10.1.5 Clear on Read/Clear on Write Modes .................................................................................................. 96
10.1.6 Global Write Method ............................................................................................................................ 97
10.1.7 Interrupt and Pin Modes....................................................................................................................... 97
10.1.8 Interrupt Structure ................................................................................................................................ 97
10.2.1 Line Clock Modes................................................................................................................................. 99
10.2.2 Sources of Clock Output Pin Signals ................................................................................................. 100
10.2.3 Line IO Pin Timing Source Selection ................................................................................................. 103
10.2.4 Clock Structures On Signal IO Pins ................................................................................................... 105
10.2.5 Gapped Clocks................................................................................................................................... 106
10.4.1 Clock Rate Adapter (CLAD)............................................................................................................... 109
10.4.2 8 kHz Reference Generation ............................................................................................................. 111
10.4.3 One-Second Reference Generation .................................................................................................. 113
10.4.4 General-Purpose IO Pins ................................................................................................................... 113
10.4.5 Performance Monitor Counter Update Details ................................................................................... 114
10.4.6 Transmit Manual Error Insertion ........................................................................................................ 115
10.5.1 Loopbacks.......................................................................................................................................... 116
10.5.2 Loss Of Signal Propagation ............................................................................................................... 118
10.5.3 AIS Logic............................................................................................................................................ 118
10.5.4 Loop Timing Mode ............................................................................................................................. 121
10.5.5 HDLC Overhead Controller ................................................................................................................ 121
10.5.6 Trail Trace .......................................................................................................................................... 121
10.5.7 BERT.................................................................................................................................................. 121
10.5.8 Fractional Payload Controller............................................................................................................. 122
10.5.9 PLCP/Fractional port pins .................................................................................................................. 122
10.5.10 Framing Modes .................................................................................................................................. 127
10.5.11 Mapping Modes.................................................................................................................................. 128
10.5.12 Line Interface Modes.......................................................................................................................... 132
10.6.1 General Description ........................................................................................................................... 134
10.6.2 Features ............................................................................................................................................. 134
10.6.6 System Interface Bus Controller ........................................................................................................ 135
S
D
P
M
HORT
IN
ROCESSOR
ER
ETAILED
LOCKS
ESET AND
LOBAL
ONITORING AND
F
Line IO.................................................................................................................................................. 66
DS3/E3 Framing and PLCP Overhead Functional Timing................................................................... 69
Internal (IFRAC) and External (XFRAC) Fractional DS3/E3 Overhead Functional Timing ................. 72
Flexible Fractional (FFRAC) DS3/E3 Overhead Interface Functinal Timing ....................................... 73
UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing........................................................... 75
Microprocessor Interface Functional Timing ........................................................................................ 87
JTAG Functional Timing....................................................................................................................... 91
Cell/Packet FIFO.................................................................................................................................. 94
Cell Processor...................................................................................................................................... 94
Packet Processor ................................................................................................................................. 95
-P
UNCTIONAL
ORT
P
........................................................................................................................................99
R
IN
ESOURCES
P
R
D
IN
P
ESOURCES
B
ESCRIPTIONS
OWER
D
US
ESCRIPTIONS
T
I
D
RDY
IMING
NTERFACE
-D
EBUGGING
..................................................................................................................109
OWN
) ............................................................................................................................. 96
................................................................................................................66
..............................................................................................................116
............................................................................................................42
..........................................................................................................107
YSTEM
........................................................................................................48
........................................................................................................96
......................................................................................................94
I
NTERFACE
4
...........................................................................134
92
96