DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 127

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DS3181

Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3181

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3181+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3181N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
10.5.10 Framing Modes
The framing modes are selected independently of the line interface modes using the PORT.CR2.FM[5:0] control
bits. Different blocks are used in different framing modes. The bit error test (BERT) function can be enabled in any
mode. The LIU, JA and line encoder/decoder blocks are selected by the line mode (LM[2:0]) code.
The “- OHM” mode, also known as “externally defined frame mode”, is a mode that allow the use of the external
frame overhead bit mask pins TOHMIn, TOHMOn and ROHMIn. This mode allows external logic to select bit
locations where another level of framing can add overhead bits such as SONET/SDH overhead bits. Payload
loopback (PLB) is disabled in this mode. The “Clear-Channel—OHM Octet aligned” modes perform octet alignment
to the overhead mask for ATM and packets and the packets become octet stuffed instead of bit stuffed.
See
Table 10-32. Framing Mode Select Bits FM[5:0]
1 1X 0X0
1 00 0X0
1 01 0X0
1 1X 001
1 1X 011
0 00 000
0 00 001
0 00 010
0 00 011
0 00 100
0 00 101
0 00 110
0 01 000
0 01 001
0 01 010
0 01 011
0 01 100
0 01 101
0 01 110
0 10 000
0 10 001
0 10 010
0 10 011
0 10 100
0 10 101
0 10 110
0 11 000
0 11 001
0 11 010
0 11 011
0 11 100
0 11 101
0 11 110
1 00 001
1 00 011
1 01 001
1 01 011
FM[5:0]
Table
10-32.
DS3 C-bit
DS3 C-bit—OHM
DS3 C-bit Internal Fractional
DS3 C-bit External Fractional
DS3 C-bit PLCP
DS3 C-bit PLCP—OHM
DS3 C-bit Flexible Fractional
DS3 M23
DS3 M23—OHM
DS3 M23 Internal Fractional
DS3 M23 External Fractional
DS3 M23 PLCP
DS3 M23 PLCP—OHM
DS3 M23 Flexible Fractional
E3 G.751
E3 G.751—OHM
E3 G.751 Internal Fractional
E3 G.751 External Fractional
E3 G.751 PLCP
E3 G.751 PLCP—OHM
E3 G.751 Flexible Fractional
E3 G.832
E3 G.832—OHM
E3 G.832 Internal Fractional
E3 G.832 External Fractional
Reserved
Reserved
E3 G.832 Flexible Fractional
DS3 Clear Channel
DS3 Clear-Channel—OHM
DS3 Clear-Channel—OHM Octet aligned
STS-1 Clear Channel
STS-1 Clear-Channel—OHM
STS-1 Clear-Channel—OHM Octet aligned
E3 Clear Channel
E3 Clear-Channel—OHM
E3 Clear-Channel—OHM Octet aligned
DESCRIPTION
127
B3ZS/AMI/UNI
UNI
B3ZS/AMI/UNI
B3ZS/AMI/UNI
B3ZS/AMI/UNI
UNI
B3ZS/AMI/UNI
B3ZS/AMI/UNI
UNI
B3ZS/AMI/UNI
B3ZS/AMI/UNI
B3ZS/AMI/UNI
UNI
B3ZS/AMI/UNI
HDB3/AMI/UNI
UNI
HDB3/AMI/UNI
HDB3/AMI/UNI
HDB3/AMI/UNI
UNI
HDB3/AMI/UNI
HDB3/AMI/UNI
UNI
HDB3/AMI/UNI
HDB3/AMI/UNI
HDB3/AMI/UNI
B3ZS/AMI/UNI
UNI
UNI
B3ZS/AMI/UNI
UNI
UNI
HDB3/AMI/UNI
UNI
UNI
LINE CODE
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM
ATM
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM
ATM
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM
ATM
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
ATM/PKT
SYSTEM
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-6
Figure 6-7
Figure 6-5
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-6
Figure 6-7
Figure 6-5
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-6
Figure 6-7
Figure 6-5
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-8
Figure 6-9
Figure 6-10
FIGURE

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