DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 100

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.1.2.2 LIU Enabled - CLAD Timing Enabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
10.2.1.2.3 LIU Disabled - CLAD Timing Disabled – no LB
In this mode, the RLCLKn pins source the clock for the receive logic and the TCLKIn pins source the clock for the
transmit logic.
10.2.1.2.4 LIU Disabled - CLAD Timing Enabled – no LB
In this mode, the RLCLKn pins source the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
10.2.2 Sources of Clock Output Pin Signals
The clock output pins can be sourced from many clock sources. The clock sources are the transmit input clocks
pins (TCLKIn), the receive clock input pins (RLCLKn), the recovered clock in the receive LIUs, and the clock
signals in the clock rate adapter circuit (CLAD). The default clock source for the receive logic is the RLCLKn pin if
the LIU is disabled; otherwise the default clock is sourced from the RX LIU clock when the RX LIU is enabled. The
default clock source for the transmit logic is the CLAD clocks.
The LIU is enabled based on the line mode bits (LM[2:0]) (See
and CLADC are located in the port configuration registers. LIUEN is not a register bit; it is a variable based on the
line mode bits. LIUEN is also zero (LIU disabled) when an “-OHM” mode is selected.
bits for LIUEN selection.
Table 10-1. LIU Enable Table
Table 10-2
configured. Putting the device in loopback will typically mux in a different clock than the normal clock source.
Table 10-2. All Possible Clock Sources Based on Mode and Loopback
Loop Timed
LM[2:0]
1XX
000
001
010
011
Normal
Normal
Normal
Normal
Normal
MODE
identifies the framer clock source and the line clock source depending on the mode that the device is
LIUEN
LLB and DLB
LOOPBACK
0
1
1
1
0
None
PLB
DLB
LLB
Any
STATUS
Disabled
Disabled
Enabled
Enabled
Enabled
LIU
RX FRAMER
Same as TX
Same as TX
RLCLKn or
RLCLKn or
RLCLKn or
RLCLKn or
SOURCE
CLOCK
RXLIU
RXLIU
RXLIU
RXLIU
100
TX FRAMER
Same as RX
Same as RX
TCLKIn or
TCLKIn or
TCLKIn or
TCLKIn or
SOURCE
CLOCK
CLAD
CLAD
CLAD
CLAD
Table
10-33). The bits LM[2:0], LBM[2:0], LOOPT
Same as RX
Same as RX
Same as RX
Same as TX
Same as TX
RLCLKn or
SOURCE
TX LINE
CLOCK
RXLIUn
Table 10-1
decodes the LM