DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 324

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 13: Remote Error Indication Interrupt Enable (REIIE) – This bit enables an interrupt if the REIL bit is set and
the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 12: Parity Error Interrupt Enable (PEIE) – This bit enables an interrupt if the PEL bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 11: Framing Error Interrupt Enable (FEIE) – This bit enables an interrupt if the FEL bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 8: Loss Of Frame Interrupt Enable (LOFIE) – This bit enables an interrupt if the LOFL bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 5: Remote Error Indication Count Interrupt Enable (REICIE) – This bit enables an interrupt if the REICL bit
is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 4: Parity Error Count Interrupt Enable (PECIE) – This bit enables an interrupt if the PECL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 3: Framing Error Count Interrupt Enable (FECIE) – This bit enables an interrupt if the FECL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 2: Remote Defect Indication Interrupt Enable (RAIIE) – This bit enables an interrupt if the RAIL bit is set and
the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: Change Of Frame Alignment Interrupt Enable (COFAIE) – This bit enables an interrupt if the COFAL bit is
set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
15
—
—
0
7
0
14
—
—
0
6
0
PLCP.RSRIE1
PLCP Receive Status Register Interrupt Enable 1
(1,3,5,7)6Ch
REICIE
REIIE
13
0
5
0
PECIE
PEIE
12
0
0
4
324
FECIE
FEIE
11
0
3
0
RAIIE
10
—
0
2
0
COFAIE
—
9
0
1
0
OOFIE
LOFIE
8
0
0
0