DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 297

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.10.5 Transmit G.832 E3 Register Map
The transmit G.832 E3 uses four registers.
Table 12-37. Transmit G.832 E3 Framer Register Map
12.10.5.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 10: Transmit GC Byte Control (TGCC) – When 0, the GC byte is inserted from the transmit HDLC controller.
When 1, the GC byte is inserted from the GC byte register.
Note: If bit TGCC is 0 and TNRC[1:0] is 01, both the GC byte and NR byte will carry the same transmit HDLC
controller (eight bits per frame period), however, the GC byte and NR byte in the same frame may or may not be
equal.
Bits 9 to 8: Transmit NR Byte Control (TNRC[1:0]) – These two bits control the source of the NR byte. Note: If
TNRC[1:0] is 01 and TGCC is 0, both the NR byte and GC byte will carry the same transmit HDLC controller (eight
bits per frame period), however, the NR byte and GC byte in the same frame may or may not be equal.
Bit 5: Transmit REI Error (TFEBE) – When automatic REI generation is defeated (AFEBED = 1), this bit is
inserted into the second bit of the MA byte.
Bit 4: Automatic REI Defeat (AFEBED) – When 0, the REI is automatically generated based upon the transmit
remote error indication (TREI) signal. When 1, the REI is inserted from the register bit TFEBE.
Bit 3: Transmit RDI Alarm (TRDI) – When automatic RDI generation is defeated (ARDID = 1), this bit is inserted
into the first bit of the MA byte.
Bit 2: Automatic RDI Defeat (ARDID) – When 0, the RDI is automatically generated based upon the received E3
alarms. When 1, the RDI is inserted from the register bit TRDI.
Bit 1: Transmit Frame Generation Control (TFGC) – When this bit is zero, the Transmit Frame Processor frame
generation is enabled. The E3 overhead positions in the incoming E3 payload will be overwritten with the internally
generated E3 overhead. When this bit is one, the Transmit Frame Processor frame generation is disabled. The E3
overhead positions in the incoming E3 payload will be passed through to error insertion. Note: The E3 overhead
periods can still be overwritten by overhead insertion.
Bit 0: Transmit Alarm Indication Signal (TAIS) – When 0, the normal signal is transmitted. When 1, the E3
output data stream is forced to all ones (AIS).
(1,3,5,7)1Ch
(1,3,5,7)1Ah
(1,3,5,7)1Eh
(1,3,5,7)18h
ADDRESS
00 = all ones.
01 = transmit from the HDLC controller.
10 = transmit from the FEAC controller.
11 = NR byte register.
Reserved
15
—
0
7
0
E3G832.TMABR
E3G832.TNGBR
E3G832.TEIR
E3G832.TCR
REGISTER
14
—
—
0
6
0
E3G832.TCR
E3 G.832 Transmit Control Register
(1,3,5,7)18h
TFEBE
E3 G.832 Transmit Control Register
E3 G.832 Transmit Error Insertion Register
E3 G.832 Transmit MA Byte Register
E3 G.832 Transmit NR and GC Byte Register
13
—
0
5
0
Reserved
AFEBED
REGISTER DESCRIPTION
12
0
0
4
297
Reserved
TRDI
11
0
3
0
ARDID
TGCC
10
0
2
0
TNRC1
TFGC
9
0
1
0
TNRC0
TAIS
8
0
0
0