DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 400

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19 REVISION HISTORY
Note: To obtain a revision history for the preliminary releases of this document, contact the factory at
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0
REVISION
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas SemiconductorCorporation.
061604
121704
010705
030205
102406
New product release (DS3184).
New product release (DS3181).
New product release (DS3182).
New product release for DS3183 on 01/21/05.
Corrected register bit map (GL.RIORR).
Clarified CP.TCR.TDSE and RCR.RDDE to state that DSS mode is only applicable for unframed
modes and bit synchronous modes.
Added clarification to Receive LIU stating that the master reference clock will use TCLKIn if no
clock exists on CLKA, B, or C.
Removed Note 3 from the DC Electrical Characteristics table since A2 fixes the problem with
TEN and REN.
Changed Input leakage for inputs with internal pullups from -300µA to -350µA.
Added lead-free package note to Ordering Information table (page 1).
Updated Package Information (Section 15).
For DS3 and STS-1 and E3 Tables:
Added TLCLK to reference clock sources for TPOS/TNEG in the Line Interface AC
Characteristics table.
Updated register bit map for PORT.INV.
Corrected wording of use of unused bits located in the Overall Register Map section.
Added I
Changed "Analog LOS Declare, RMON = 0" from -24dB max to -24dB typ, and added
Changed "Analog LOS Clear, RMON = 0" from -17dB min to -17dB typ, and added -16dB min.
-28dB max.
DD
measurements for DS3181/DS3182/DS3183.
© 2006 Maxim Integrated Products
400
DESCRIPTION
DS3181/DS3182/DS3183/DS3184
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.