DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 203

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11-1. Global and Test Register Address Map
Each port has a relative address range of 040h to 1FFh. The lower 000h to 03Fh address range is used for global,
test and reserved registers. The following table is a map of the registers for each port. The address offset is from
the start of each port range of 000h, 200h, 400h and 600h. In a DS3183, writes to registers in port 4 will be ignored
and reads from port 4 registers will read back zero values. Similarly, in a DS3181, writes to registers in port 2 will
be ignored and reads from port 2 will read back zero values.
Note: The
any design blocks. The
blocks.
Table 11-2. Per-Port Register Address Map
ADDRESS
ADDRESS
040–1FF
0C0–0CF
0D0–0DF
0A0–0AF
0B0–0BF
0E8–0EF
08C–08F
0E0–0E7
0F0–0FF
000–01F
020–02F
038–03F
040–1FF
200–23F
240–3FF
400–43F
440–5FF
600–63F
640–6FF
OFFSET
040–05F
060–07F
080–08B
090–09F
030–037
Port 1
RDY
signal will not go active if the user attempts to read or write unused ports or unused registers not assigned to
Global Registers, Section
Unused
UTOPIA/POS-PHY Transmit System Bus, Section
UTOPIA/POS-PHY Receive System Bus, Section
Port 1 Register Map
Test Registers
Port 2 Register Map
Test Registers
Port 3 Register Map
Unused
Port 4 Register Map
Port Common Registers
BERT
Reserved
B3ZS/HDB3 Transmit Line Encoder
B3ZS/HDB3 Receive Line Decoder
HDLC Transmit
HDLC Receive
FEAC Transmit
FEAC Receive
Reserved
Trail Trace Transmit
Trail Trace Receive
240–3FF
Port 2
RDY
signal will go active if the user writes or reads reserved registers or unused registers within design
DESCRIPTION
440–5FF
Port 3
DESCRIPTION
12.1
640–7FF
Port 4
203
ADDRESS
100– 117
1A0–1BF
1C0–1FF
OFFSET
118–11F
120–13F
140–147
148–14F
150–15F
160–17F
180–18F
190–19F
12.3.2
12.3
Reserved
DS3/E3 Framer Transmit
DS3/E3 Framer Receive
DS3/E3 Fractional Transmit
DS3/E3 Fractional Receive
DS3/E3 PLCP Transmit
DS3/E3 PLCP Receive
UTOPIA/POS-PHY Transmit FIFO
UTOPIA/POS-PHY Receive FIFO
Transmit Cell/Packet Processor
Receive Cell/Packet Processor
DESCRIPTION