DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 18
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DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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3.4 Receive PLCP Framer Features
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3.5 Receive Cell Processor Features
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3.6 Receive Packet Processor Features
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Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of
frame alignment (COFA), receipt of B3ZS/HDB3 code words, DS3 application ID bit, DS3 M23/C-bit format
mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits
HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
FEAC port for DS3 FEAC channel
16-byte Trail Trace Buffer port for G.832 trail access point identifier
DS3 M23 C bits and stuff bits configurable as payload or overhead, stored in registers for software inspection
Most framing overhead fields presented on the receive overhead port
Support for internal and external subrate DS3/E3 control (Fractional DS3/E3)
PLCP frame synchronization
C1 cycle/stuff counter interpretation
Detection of out of frame (OOF), BIP-8 errors, FEBE and RAI (Yellow Signal)
Frame timing can be presented on the GPIO2 output pin or used as the transmit PLCP reference
All path overhead fields presented on the PLCP receive overhead port
HDLC port for data link messages on F1, M1 or M2 bytes
Trail Trace port for trace messages on F1 byte
HEC-based cell delineation within the DS3/E3 frame, the PLCP frame, an externally defined frame, or the
entire line bandwidth
Cell descrambling using the self-synchronizing scrambler (x
Distributed Sample Scrambler (DSS) for clear-channel ATM (cell-based physical layer)
HEC error detection and correction; HEC discard
Filtering of idle, unassigned and/or invalid cells (provisionable)
Header pattern comparison vs. 32-bit header pattern and mask registers; counting of matching or non-
matching cells; discard of matching or non-matching cells
Four-cell Receive FIFO
Controls include enables/disables/settings for: cell processing, coset polynomial addition, error correction,
erred cell extraction, cell descrambling, idle/unassigned/invalid cell filtering, header pattern match
counting/discarding, LCD integration time
Status fields include: out of cell delineation (OCD), loss of cell delineation (LCD) and receipt of idle,
unassigned, invalid, erred, corrected or header-pattern-match cells
Performance monitoring counters for forwarded cells, corrected cells, uncorrectable cells, header pattern
match/no-match cells, and filtered idle/unassigned/invalid cells
Octet alignment option for externally defined frame formats
Packet descrambling using the self-synchronizing scrambler (x
Flag detection, packet delineation, and inter-frame fill discard (flags and all-ones)
Packet abort detection and accumulation
Bit or octet destuffing
FCS checking (16-bit or 32-bit), error accumulation, and FCS discard
Packet size checking vs. programmable minimum and maximum size registers
Abort declaration for packets with non-integral number of bytes
Controls include enables/disables/settings for: packet processing, descrambling, 16/32-bit FCS, filtering of FCS
erred packets, FCS discard, minimum/maximum packet size
Status fields include: receipt of FCS erred packet, aborted packet, size violation packet, non-integer-length
packets
Performance monitoring counters for forwarded packets, forwarded bytes, aborted bytes, FCS erred packets,
aborted packets, size violation packets (min, max, non-integer-length)
Octet alignment with octet destuffing option for externally defined frame formats
18
43
+1) for ATM over DS3/E3
43
+1)
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