DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 108

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-10. Reset and Power-Down Sources
Register bit states - F0: Forced to 0, F1: Forced to 1, 0: Set to 0, 1: Set to 1, X: Don’t care
0
1
1
1
1
1
1
1
1
1
The reset signals in the device are asynchronous so they no not require a clock to put the logic into the reset state.
Clock signals may be needed to make the logic come out of the reset state.
The power-down function disables the appropriate clocks to cause the logic to generate a minimum of power. It
also puts the LIU circuits into the power-down mode. Note that the UTOPIA/POS-PHY system interface logic
cannot be powered down, the clocks cannot be stopped. The 8KREF and ONESEC circuits can be powered down
by disabling the 8KREF source. The CLAD can also be powered down by disabling it.
After a global reset, all of the control and status registers in all ports are set to their default values and all the other
flops are reset to their reset values. The global register GL.CR1.RSTDP, and the port register PORT.CR1.RSTDP
and PORT.CR1.PD bits in all ports, are set after the global reset. A valid initialization sequence would be to clear
the PORT.CR1.PD bits in the ports that are to be active, write to all of the configuration registers to set them in the
desired modes, then clear the GL.CR1.RSTDP and PORT.CR1.RSTDP bits. This would cause the logic in the
ports to start up in a repeatable sequence. The device can also be initialized by clearing the GL.CR1.RSTDP,
PORT.CR1.RSTDP and PORT.CR1.PD them writing to all of the configuration registers to set them in the desired
modes, and clearing all of the latched status bits. The second initialization scheme could cause the device to
temporarily go into modes of operation that were not requested, but will quickly go into the requested modes of
operation.
Some of the IO pins are put in a known state at reset. The transmit LIU outputs TXPn and TXNn are quiet and will
not drive positive or negative pulses. The global IO pins (GPIO[7:0]) are set as inputs at global reset. The port
output pins (TLCLKn, TPOSn/TDATn, TNEGn/TOHMOn, TOHCLKn, TOHSOFn, TPOHSOFn/TSOFOn/TDENn/
TFOHENOn,
RPOHSOFn/RSOFOn/RDENn/RFOHENOn, RPOHCLKn/RCLKOn/RGCLKn) are driven low at global or port reset
and should stay low until after the port power-down PORT.CR1.PD and port data path reset PORT.CR1.RSTDP
bits are cleared. The CLAD clock pins CLKA, CLKB and CLKC are the LIU reference clock inputs at global reset.
The system interface three-state output pins (TDXA[1]/TPXA, TSPA, RDATA[31:0], RPRTY, RDXA[1]/RPXA/RSX,
RSOX, REOP, RVAL, RMOD[1:0], RERR) are in the high impedance and the system interface output pins
(TDXA[4:2],RDXA[4:2]) are driven low at global reset. The processor port three-state output pins (D[15:0], RDY,
INT) are forced into the high impedance state when the RST pin is active, but not when the GL.CR1.RST bit is
active.
PIN
Forced: Internally controlled
Set: User controlled
F0
1
0
0
0
0
0
0
0
0
F1
F1
1
1
1
0
0
0
0
0
REGISTER BITS
TPOHCLKn/TCLKOn/TGCLKn,
F0
F0
1
0
0
1
0
0
0
0
F1
F1
F1
X
X
F1
1
1
0
0
F1
F1
F1
1
0
F1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
INTERNAL SIGNALS
ROHn,
108
1
1
1
0
0
1
0
0
0
0
ROHCLKn,
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
1
0
ROHSOFn,
RPOHn/RSERn,