DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 68
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 8-4. RX Line IO HDB3 Functional Timing Diagram
8.3.1.3
The TDATn pin is available when the line interface is in the UNI mode and the transmit line pins are enabled. The
TOHMOn and TOHMIn pins are available when the framer is in one of the “- OHM” modes and the transmit line
pins are enabled. The line interface is forced into the UNI mode when the framer is in one of the “- OHM” modes.
The TOHMIn pin is used to control the insertion of gaps in the data by stopping the internal formatters and data
sources. These gaps are inserted where external logic will add more overhead bits to the signal. The TOHMOn
signal is delayed from the TOHMIn signal by three clock periods. The TOHMOn signal aligns to the TDATn signal
and is high when internal framing and signal source has stopped inserting data. The TDATn signal should be
ignored when TOHMOn is high. In the “- OHM Octet” framing modes, the first payload bit after the TOHMOn signal
goes low is the MSB (Bit 1) of a payload Octet.
The TDATn and TOHMOn signals change a small delay after the positive edge of the reference clock signal if the
clock pin is not inverted, other wise they change after the negative edge. The TOHMIn signal is sampled at the
rising edge of the reference clock signal if the clock pin is not inverted; otherwise it is sampled at the negative
edge. The TLCLKn clock pin is the clock reference typically used for the TDATn, TOHMOn and TOHMIn signals,
but they can be time referenced to the TCLKIn, TCLKOn, RLCLKn or RCLKOn clock pins. The TDATn, TOHMOn,
and TOHMIn pins can be inverted. See
Figure 8-5. TX Line IO UNI OHM Functional Timing Diagram
Figure 8-6. TX Line IO UNI Octet Aligned OHM Functional Timing Diagram
TOHMO
TLCLK
TOHMI
(RX DATA)
TOHMO
TDAT
(RX LINE)
TLCLK
TOHMI
TDAT
RLCLK
RNEG
RPOS
RXN
RXP
UNI Mode Transmit Pin Functional Timing
B6 B7 B8
Octet n
0 V
BIAS V
+
EXT OH BIT LOCATIONS
-
TDAT GAP FOR EXT OVERHEAD INSERTION
Figure 8-5
B
B
B
B
and
Figure 8-6
68
B1 B2 B3 B4 B5 B6 B7 B8 B1
V
V
V
V
ATM Cell /Packet Octet n+1
HDB3 CODEWORD
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