DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 346

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.14.2.2 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Receive DSS Descrambling Enable (RDDE) – When 0, self-synchronous descrambling is enabled. When
1, DSS descrambling is enabled. DSS mode is only applicable for un-framed or clear channel framing and bit
synchronous modes. This bit is ignored if descrambling is disabled. Note: In byte synchronous and cell pass-
through modes, self-synchronous descrambling is enabled regardless of the setting of this bit.
Bit 14: Receive DQDB HEC Processing Enable (RDHE) – When 0, the HEC is calculated over all four-header
bytes. When 1, only the last three header bytes are used for HEC calculation.
Bit 13: Receive Errored Cell Extraction Disable (RECED) – When 0, errored cells are extracted. When 1,
errored cells are passed on.
Bits 12 to 11: Receive Header Pattern Comparison Mode (RHPM[1:0]) – These two bits control the operation of
the header pattern comparison function.
Bit 10: Receive Idle Cell Filtering Disable (RICFD) – When 0, idle cells are discarded. When 1, idle cells are
passed on.
Bit 9: Receive Unassigned Cell Filtering Enable (RUCFE) – When 0, unassigned cells are passed on. When 1,
unassigned cells are counted and discarded.
Bit 8: Receive Invalid Cell Filtering Enable (RICFE) – When 0, invalid cells are passed on. When 1, invalid cells
are discarded.
Bits 7 to 6: Receive Error Monitoring Required OK Cells (RROC[1:0]) – These two bits indicate the number of
good cells required to transition from the "Detection" state to the "Correction" state, which enables single bit
correction of the header (see
Bit 5: Receive HEC Coset Polynomial Addition Disable (RCPAD) – When 0, the HEC coset polynomial addition
is performed prior to checking the HEC byte. When 1, HEC coset polynomial addition is disabled
Bit 4: Receive Header Error Correction Disable (RHECD) – When 0, single bit header error correction is
enabled. When 1, header error correction is disabled and all errors are treated as an un-correctable error.
Bit 3: Receive Cell Header Descrambling Enable (RHDE) – When 0, only the cell payload will be descrambled.
When 1, the entire data stream (cell header and payload) is descrambled. This bit is ignored if descrambling is
disabled or DSS descrambling is enabled. When cell pass-through mode is enabled, the entire data stream will be
descrambled if descrambling is enabled.
Bit 2: Receive Descrambling Disable (RDD) – When 0, descrambling is performed. When 1, descrambling is
disabled.
00 = Count match: Cells that match the header pattern are counted.
01 = Count no match - Cells that do not match the header pattern are counted.
10 = Discard match - Cells that match the header pattern are counted and discarded.
11 = Discard no match - Cells that do not match the header pattern are counted and discarded.
00 = 1 good cell is required.
01 = 2 good cells are required.
10 = 4 good cells are required.
11 = 8 good cells are required.
RROC1
RDDE
15
0
7
0
RROC0
RDHE
14
0
6
0
Figure
CP.RCR1
Cell Processor Receive Control Register 1
(1,3,5,7)C0h
10-28).
RECED
RCPAD
13
0
5
0
RHECD
RHPM1
12
0
0
4
346
RHPM0
RHDE
11
0
3
0
RICFD
RDD
10
0
2
0
RUCFE
RBRE
9
0
1
0
RICFE
RPTE
8
0
0
0