DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 79
DS3181
Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3181
Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 8-31
the ATM device polls PHY port 'N'. On clock edge 3, PHY port 'N' indicates to the ATM device that it can accept cell
data by asserting TPXA. On clock edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device
starts a cell transfer to PHY port 'N' by asserting TEN, placing the first byte of cell data on TDATA, and asserting
TSOX to indicate the transfer of the first byte of the cell. On clock edge 7, the ATM device deasserts TSOX as it
continues to place additional bytes of the cell on TDATA. On clock edge 11, the ATM device polls PHY port 'M'. On
clock edge 12, the ATM device polls PHY port 'N'. On clock edge 13, PHY port 'M' indicates that it can accept the
transfer of a complete cell. On clock edge 14, PHY port 'N' indicates that it cannot accept the transfer of a complete
cell. On clock edge 16, the ATM device deselects PHY port 'N' and selects PHY port 'M' by deasserting TEN and
placing PHY port 'M's address on TADR. On clock edge 17, the ATM device starts the transfer of a cell to PHY port
'M' by asserting TEN, placing the first byte of cell data on TDATA, and asserting TSOX to indicate the transfer of
the first byte of the cell. On clock edge 18, the ATM device deasserts TSOX as it continues to place additional
bytes of the cell on TDATA.
Figure 8-31. UTOPIA Level 3 Transmit Multiple Cell Transfer Polled Mode
Figure 8-32
PHY port 'N' indicates to the ATM device that it has a complete cell ready for transfer by asserting RPXA. On clock
edge 5, the ATM device selects PHY port 'N'. On clock edge 6, the ATM device indicates to PHY port 'N' that it is
ready to accept a complete cell transfer by asserting REN. On clock edge 8, PHY port 'N' starts a cell transfer by
placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell.
On clock edge 9, PHY port 'N' deasserts RSOX as it continues to place additional bytes of the cell on RDAT. On
clock edge 11, the ATM device polls PHY device 'N'. On clock edge 12, PHY port 'M' indicates to the ATM device
that it has a complete cell ready for transfer by asserting RPXA. On clock edge 12, PHY port 'N' indicates to the
ATM device that it does not have a complete cell ready for transfer by deasserting RPXA. On clock edge 15, the
ATM device deselects PHY port 'N' and selects PHY port 'M' by deasserting REN and placing PHY port 'M's
address on RADR. On clock edge 16, the ATM device asserts REN. On clock edge 17, PHY port 'N' stops
transferring cell data. On clock edge 18, PHY port 'M' starts a cell transfer by placing the first byte of cell data on
RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell. On clock edge 19, PHY port 'M'
deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Transfer
TDATA
Cell To:
TADR
TSOX
TCLK
TPXA
TEN
M
K
X
shows a multiport transmit-interface multiple cell transfer to different PHY devices. On clock edge 1,
shows a multiport receive-interface multiple cell transfer from different PHY ports. On clock edge 3,
1
N
L
X
2
O
M
X
3
N
P
X
4
Q
O
X
5
N
P
X
6
H1
Q
R
7
H2
X
J
8
H3
K
R
9
…
…
…
79
10
N
P43
L
J
11
P44
M
K
12
P45
N
L
13
P46
M
O
14
P47
P
N
15
P48
Q
O
16
M
P
X
17
H1
R
Q
18
M
H2
X
J
19
H3
R
K
20
P1
L
J
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