DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 136

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-24. Byte Reordered Packet Format in 16-Bit Mode
Bit 15
10.6.6.4 UTOPIA Level 2, Transmit Side
In UTOPIA Level 2, an ATM layer device pushes cells across the system interface. The ATM layer device polls the
individual ports of the DS318x to determine which ports have space available for a cell, and selects a port for cell
transfer. More than one PHY layer device can be present on a UTOPIA Level 2 bus. Whether or not the HEC byte
is transferred with the cells is programmable.
The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit address (TADR[4:0]),
transmit enable (TEN), and a transmit data bus consisting of transmit data (TDATA[31:0]), transmit parity (TPRTY),
and transmit start of cell (TSOX). It outputs transmit direct cell available (TDXA) and transmit polled cell available
(TPXA) signals. The transmit data bus is used to transfer cell data whenever one of the ports is selected for cell
data transfer. TSOX is asserted during the first transfer of a cell, cell data is transferred on TDATA, and the data
bus parity is indicated on TPRTY. All signals are sampled or updated using TSCLK. The TDXA and TPXA signals
are used to indicate when the Transmit FIFO has space available for a programmable number of cells. There is a
TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has more space
available than a programmable number of cells. TDXA goes low when the associated port's Transmit FIFO is full
(does not have space for another cell). TPXA reflects the current status of a port's TDXA signal when the port is
polled. The TPXA signal is tri-stated unless one of the ports is being polled for FIFO fill status.
10.6.6.5 UTOPIA Level 3, Transmit Side
In UTOPIA Level 3, the ATM layer device pushes cells across the system interface. The ATM layer device polls the
individual ports of the DS318x to determine which ports have space available for a cell, and selects a port for cell
transfer. Only one PHY layer device can be present on a UTOPIA Level 3 bus. Whether or not the HEC byte is
transferred with the cells is programmable.
The Transmit System Interface Bus Controller accepts a transmit clock (TSCLK), transmit address (TADR[7:0]),
transmit enable (TEN), and a transmit data bus consisting of transmit data (TDATA[31:0]), transmit parity (TPRTY),
and transmit start of cell (TSOX). It outputs transmit direct cell available (TDXA) and transmit polled cell available
(TPXA) signals. The transmit data bus is used to transfer cell data whenever one of the ports is selected for cell
data transfer. TSOX is asserted during the first transfer of a cell, cell data is transferred on TDATA, and the data
bus parity is indicated on TPRTY. All signals are sampled or updated using TSCLK. The TDXA and TPXA signals
are used to indicate when the Transmit FIFO has space available for a programmable number of cells.
There is a TDXA for each port in the device. TDXA goes high when the associated port's Transmit FIFO has more
space available than a programmable number of cells. TDXA goes low when the associated port's Transmit FIFO
is full (does not have space for another cell). TPXA reflects the current status of a port's TDXA signal when the port
is polled. The TPXA signal is always driven.
10.6.6.6 UTOPIA Level 2, Receive Side
In UTOPIA Level 2, the ATM layer device pulls cells across the system interface. The ATM layer device polls the
individual ports to determine which ports have cells available, and selects a port for cell transfer. More than one
PHY layer device can be present on a UTOPIA Level 2 bus. Whether or not the HEC byte is transferred with the
cells is programmable.
The Receive System Interface Bus Controller accepts a receive clock (RSCLK), receive address (RADR[4:0]), and
receive enable (REN). It outputs a receive data bus consisting of receive data (RDATA[31:0]), receive parity
(RPRTY), and receive start of cell (RSOX), as well as, receive direct cell available (RDXA) and receive polled cell
Byte 2n-2
Byte 2n
Byte 2
Byte 4
•
•
•
Byte 2n-3
Byte 2n-1
Byte 1
Byte 3
•
•
•
Bit 0
(n-1)
2
n
1
nd
st
th
th
Transfer
Transfer
Transfer
Transfer
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DS3181/DS3182/DS3183/DS3184