DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 182

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

See
Figure 10-46. HDLC Controller Block Diagram
10.11.2 Features
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10.11.3 Transmit FIFO
The Transmit FIFO block contains memory for 256 bytes of data with data status information and controller circuitry
for reading and writing the memory. The Transmit FIFO controller functions include filling the memory, tracking the
memory fill level, maintaining the memory read and write pointers, and detecting memory overflow and underflow
conditions. The Transmit FIFO receives data and status from the microprocessor interface, and stores the data
along with the data status information in memory. The Transmit Packet Processor reads the data and data status
information from the Transmit FIFO. The Transmit FIFO also outputs FIFO fill status (empty/data storage
available/full) via the microprocessor interface. All operations are byte based. The Transmit FIFO is considered
empty when its memory does not contain any data. The Transmit FIFO is considered to have data storage
available when its memory has a programmable number of bytes or more available for storage. The Transmit FIFO
is considered full when it does not have any space available for storage. The Transmit FIFO accepts data from the
register interface until full. If the Transmit FIFO is written to while the FIFO is full, the write is ignored, and a FIFO
overflow condition is declared. The Transmit Packet Processor reads the Transmit FIFO. If the Transmit Packet
Processor attempts to read the Transmit FIFO while it is empty, a FIFO underflow condition is declared.
10.11.4 Transmit HDLC Overhead Processor
The Transmit HDLC Overhead Processor accepts data from the Transmit FIFO, performs bit reordering, FCS
processing, stuffing, packet abort sequence insertion, and inter-frame padding.
A byte is read from the Transmit FIFO with a packet end status. When a byte is marked with a packet end
indication, the output data stream will be padded with FFh and marked with a FIFO empty indication if the Transmit
Clock Rate
Programmable inter-frame fill – The inter-frame fill between packets can be all 1’s or flags.
Programmable FCS generation/monitoring – A FCS-16 can be generated and appended to the end of the
packet, and the FCS can be checked and removed from the end of the packet.
Programmable bit reordering – The packet data can be can be output MSB first or LSB first from the FIFO.
Programmable data inversion – The packet data can be inverted immediately after packet processing on the
transmit, and immediately before packet processing on the receive.
Fully independent transmit and receive paths
Fully independent Line side and register interface timing – The data storage can be read from or written to
via the microprocessor interface while all line side clocks and signals are inactive, and read from or written to
via the line side while all microprocessor interface clocks and signals are inactive.
Receive
Transmit
DS3/E3
Figure 10-46
DS3/E3
Adapter
LIU
LIU
for the location of HDLC controllers within the DS318x devices.
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
Access Port
JTAG Test
FEAC
DS3 / E3
Receive
Framer
Formatter
DS3 / E3
Transmit
Buf f er
Trace
Trail
HDLC
UA1
GEN
182
TX FRAC/
PLCP
RX FRAC/
PLCP
Processor
Processor
Rx Packet
Processor
Processor
Tx Packet
RX BERT
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx