DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 12

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
Table 10-39. Repetitive Pattern Generation ............................................................................................................ 194
Table 10-40. Transformer Characteristics ............................................................................................................... 199
Table 10-41. Recommended Transformers............................................................................................................. 200
Table 11-1. Global and Test Register Address Map ............................................................................................... 203
Table 11-2. Per-Port Register Address Map ........................................................................................................... 203
Table 12-1. Global Register Bit Map........................................................................................................................ 204
Table 12-2. System Interface Bit Map ..................................................................................................................... 205
Table 12-3. Port Register Bit Map ........................................................................................................................... 205
Table 12-4. BERT Register Bit Map ........................................................................................................................ 206
Table 12-5. LINE Register Bit Map .......................................................................................................................... 206
Table 12-6. HDLC Register Bit Map ........................................................................................................................ 207
Table 12-7. FEAC Register Bit Map ........................................................................................................................ 208
Table 12-8. Trail Trace Register Bit Map................................................................................................................. 208
Table 12-9. T3 Register Bit Map.............................................................................................................................. 209
Table 12-10. E3 G.751 Register Bit Map................................................................................................................. 210
Table 12-11. E3 G.832 Register Bit Map................................................................................................................. 211
Table 12-12. Clear-Channel Register Bit Map......................................................................................................... 212
Table 12-13. Fractional Register Bit Map ................................................................................................................ 212
Table 12-14. PLCP Register Bit Map....................................................................................................................... 213
Table 12-15. FIFO Register Bit Map........................................................................................................................ 214
Table 12-16. Transmit Cell Processor Register Bit Map ......................................................................................... 215
Table 12-17. Transmit Packet Processor Register Bit Map .................................................................................... 216
Table 12-18. Receive Cell Processor Register Bit Map .......................................................................................... 216
Table 12-19. Receive Packet Processor Register Bit Map ..................................................................................... 217
Table 12-20. Global Register Map........................................................................................................................... 219
Table 12-21. Transmit System Interface Register Map ........................................................................................... 227
Table 12-22. Receive System Interface Register Map ............................................................................................ 229
Table 12-23. Per-Port Common Register Map ........................................................................................................ 231
Table 12-24. BERT Register Map............................................................................................................................ 242
Table 12-25. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map ..................................................... 251
Table 12-26. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map ...................................................... 252
Table 12-27. Transmit Side HDLC Register Map .................................................................................................... 256
Table 12-28. Receive Side HDLC Register Map ..................................................................................................... 260
Table 12-29. FEAC Transmit Side Register Map .................................................................................................... 264
Table 12-30. FEAC Receive Side Register Map ..................................................................................................... 267
Table 12-31. Transmit Side Trail Trace Register Map............................................................................................. 270
Table 12-32. Trail Trace Receive Side Register Map.............................................................................................. 272
Table 12-33. Transmit DS3 Framer Register Map .................................................................................................. 276
Table 12-34. Receive DS3 Framer Register Map ................................................................................................... 279
Table 12-35. Transmit G.751 E3 Framer Register Map .......................................................................................... 289
Table 12-36. Receive G.751 E3 Framer Register Map ........................................................................................... 291
Table 12-37. Transmit G.832 E3 Framer Register Map .......................................................................................... 297
Table 12-38. Receive G.832 E3 Framer Register Map ........................................................................................... 300
Table 12-39. Transmit Clear-Channel Register Map............................................................................................... 309
Table 12-40. Receive Clear-Channel Register Map................................................................................................ 310
Table 12-41. Fractional Transmit Side Register Map .............................................................................................. 312
Table 12-42. Receive Side Register Map................................................................................................................ 314
Table 12-43. Transmit Side PLCP Register Map .................................................................................................... 316
Table 12-44. Receive Side PLCP Register Map ..................................................................................................... 320
Table 12-45. Transmit FIFO Register Map.............................................................................................................. 331
Table 12-46. Receive FIFO Register Map............................................................................................................... 335
Table 12-47. Transmit Cell Processor Register Map............................................................................................... 338
Table 12-48. HEC Error Mask ................................................................................................................................. 341
Table 12-49. Receive Cell Processor Register Map................................................................................................ 345
Table 12-50. Transmit Packet Processor Register Map.......................................................................................... 357
Table 12-51. Receive Packet Processor Register Map........................................................................................... 362
Table 13-1. JTAG Instruction Codes ....................................................................................................................... 375
Table 13-2. JTAG ID Codes .................................................................................................................................... 376
Table 14-1. Pin Assignment Breakdown ................................................................................................................. 377
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