DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 148

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
tagged with an abort indication, and the packet size violation count is incremented. In octet aligned mode, after
destuffing is completed, the 8-bit parallel data stream is passed on to packet size checking. If packet processing is
disabled, destuffing is not performed.
Packet size checking checks each packet for a programmable maximum and programmable minimum size. As the
packet data comes in, the total number of bytes is counted. If the packet length is below the minimum size limit, the
packet is marked with an aborted indication, and the packet size violation count is incremented. If the packet length
is above the maximum size limit, the packet is marked with an aborted indication, the packet size violation count is
incremented, and all packet data is discarded until a packet start is received. The minimum and maximum lengths
include the FCS bytes, and are determined after destuffing has occurred. If packet processing is disabled, packet
size checking is not performed.
FCS error monitoring checks the FCS and aborts errored packets. If a FCS error is detected, the FCS errored
packet count is incremented and the packet is marked with an aborted indication. The FCS type (16-bit or 32-bit) is
programmable. If FCS processing or packet processing is disabled, FCS byte extraction is not performed.
FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet.
If FCS processing or packet processing is disabled, FCS byte extraction is not performed.
Bit reordering changes the bit order of each byte. If bit reordering is enabled, the incoming 8-bit data stream
DT[7:0] with DT[7] being the MSB and DT[0] being the LSB is rearranged so that the MSB is in DT[0] and the LSB
is in DT[7] of the outgoing FIFO data stream DT[7:0]. In bit synchronous mode, DT[7] is the first bit received.
Once all packet processing has been completed, the 8-bit parallel data stream is demultiplexed into a 32-bit parallel
data stream and passed on to the Receive FIFO.
10.7.7 FIFO
10.7.7.1 Transmit FIFO
The Transmit FIFO block contains memory for 64 32-bit data words. The Transmit FIFO separates the transmit
system interface timing from the transmit physical interface timing. The Transmit FIFO functions include filling the
memory, tracking the memory fill level, maintaining the memory read and write pointers, and detecting memory
overflow and underflow conditions. The number of data transfers that can occur after the Transmit FIFO "full"
indication is deasserted is programmable. The Transmit FIFO port address used for selection and polling by the
Transmit System Interface Bus Controller is programmable. In system loopback, the data from the Transmit FIFO is
looped back to the Receive FIFO, and a FIFO empty indication is passed on to the Transmit Cell/Packet Processor.
In cell processing mode, all operations are cell based. The Transmit FIFO is considered empty when it does not
contain any data. The Transmit FIFO is considered "almost empty" when it does not contain a cell. The Transmit
FIFO is considered "almost full" when it does not have space available to store a programmable number of cells.
The Transmit FIFO is considered full when it does not have space available for a complete cell. When the Transmit
FIFO level drops below the “almost full” indication, the TDXA[n] is asserted. The Transmit FIFO accepts cell
transfers from the Transmit System Interface Bus Controller until it is full. If a start of cell is received while full, the
cell is discarded and a FIFO overflow condition is declared. Once a FIFO overflow condition is declared, the
Transmit FIFO will discard cell data until a start of cell is received while the FIFO has more space available than
the "almost full" level. If the Transmit FIFO receives cell data other than a start of cell after a complete cell has
been received, an invalid transfer is declared and all cell data is discarded until a start of cell is received. If a start
of cell is received before a previous cell transfer has been completed, the current cell is discarded and a short
transfer is declared. The new cell is processed normally. If the Transmit Cell Processor attempts a read while the
Transmit FIFO is empty, a FIFO underflow condition is declared. Once a FIFO underflow condition is declared, the
Transmit FIFO data will be discarded until a start of cell is received.
In packet processing mode, all operations are byte based. The Transmit FIFO is considered empty when its
memory does not contain any data. The Transmit FIFO is considered "almost empty" when its memory does not
contain a packet end and there is a programmable number of bytes or less stored in the memory. The Transmit
FIFO is considered "almost full" when its memory has a programmable number of bytes or less available for
storage. When the Transmit FIFO has more bytes available for storage than the “almost full” level the TDXA[n] or
TPXA pin will be asserted to signal to the POS device that it is ready to receive more packet data. The Transmit
FIFO is considered full when it does not have any space available for storage. When the Transmit FIFO is full, the
TDXA[n] pin will be deasserted. The Transmit FIFO accepts data from the Transmit System Interface Bus
Controller until full. If a start of packet or short packet (32-bit data word with a start of packet and end of packet) is
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