DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 233

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Transmit Line IO Signal Enable (TLEN). This bit is used to enable to transmit line interface output pins
TLCLKn, TPOSn/TDATn and TNEGn.
Bit 14: Transmit LIU Tri-State (TTS) This bit is used to tri-state the transmit TXPn and TXNn pins. The LIU is still
powered up when the pins are tri-stated. It has no effect when the LIU is disabled and powered down.
Bit 13: Receive LIU Monitor Mode (RMON) This bit is used to enable the receive LIU monitor mode pre-amplifier.
Enabling the pre-amplifier adds about 20 dB of linear amplification for use in monitor applications where the signal
has been reduced 20 dB using resistive attenuator circuits.
Bit 12: Transmit LIU LBO (TLBO) This bit is used enable the transmit LBO circuit which causes the transmit
signal to have a wave shape that approximates about 225 feet of cable. This is used to reduce near end crosstalk
when the cable lengths are short. This signal is only valid in DS3 and STS-1 LIU modes.
Bit 11: Receive ATM Cell Delineation Verify 8 Enable (RCDV8). This bit determines the number of good cells
required for the ATM cell delineator state machine to transition from the “Verify” state to the “Update” state. This
setting also determines how many valid cells required to clear the OCD status bit.
Bits 10 to 8: Port Interface Mode (LM[2:0]). The LM[2:0] bits select main port interface operational modes. The
default state disables the LIU and the JA. See
Bit 7: Receive Cell Delineator Disable (RCDIS). This bit determines if the ATM cell delineator in the ATM cell
processor is active in PLCP modes. This ATM cell delineator in the ATM cell processor is always active in non-
PLCP ATM cell modes.
Bit 6: POS-PHY Mode Cell Processor Enable (PMCPE). This bit determines the associated transmit and receive
port interface processing (cell/packet) to be performed in the POS-PHY mode. It is only active in POS-PHY mode
when PLCP is not enabled. When PLCP is enabled in POS-PHY mode, cell processing is performed.
Bits 5 to 0: Framing mode (FM[5:0]). The FM[5:0] bits select main framing operational modes. Default: DS3 C-bit.
See
Table
0 = Disable, force outputs low
1 = Enable normal operation
0 = TXPn and TXNn driven
1 = TXPn and TXNn tri-stated
0 = Disable the 20 dB pre-amp
1 = Enable the 20 dB pre-amp
0 = TXPn and TXNn have full amplitude signals
1 = TXPn and TXNn signals approximate 225 feet of cable
0 = Six valid ATM cells are required (typical for framed cells)
1 = Eight valid ATM cells are required (typical for unframed cells)
0 = ATM cell delineation is determined in the ATM cell processor
1 = ATM cell delineation is determined in the PLCP framer
Note: RCDIS = 1 is not a recommended mode.
0 = Packet processing will be performed
1 = Cell processing will be performed
10-32.
RCDIS
TLEN
15
0
7
0
PMCPE
TTS
14
0
6
0
PORT.CR2
Port Control Register 2
(0,2,4,6)42h
RMON
FM5
13
0
5
0
Table
TLBO
10-33.
FM4
12
0
0
4
233
RCDV8
FM3
11
0
3
0
LM2
FM2
10
0
2
0
LM1
FM1
9
0
1
0
FM0
LM0
8
0
0
0