DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 341

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Transmit HEC Error Mask (THEM[7:0]) –These bits control the error insertion into the HEC byte.
Setting these bits will corrupt the associated HEC bit during cell error insertion. Based on the value set in this
register, the far end will detect three types of errors: an error in the HEC, a single bit error in the header, or multiple
bit errors in the header. Default (THEM[7:0] = 00h) is no error inserted. If a single bit error is selected, the table
below also shows which bit of the 32-bit HEC header will be corrupted.
inserted by a specific mask value. Note: If a single bit error is inserted in the HEC, and the far-end has single bit
error correction enabled, this will cause the indicated header bit to be corrupted.
Table 12-48. HEC Error Mask
0Ch-0Dh
17h-1Dh
2Dh-30h
09h-0Ah
01h-02h
05h-06h
11h-14h
21h-29h
VALUE
0Bh
0Eh
1Eh
2Ah
2Bh
2Ch
03h
04h
07h
08h
0Fh
10h
15h
16h
1Fh
20h
31h
THEM7
15
—
0
7
0
ERROR
Single
Single
Single
Single
Single
Single
Single
Single
Single
TYPE
HEC
Multi
HEC
Multi
HEC
Multi
Multi
Multi
HEC
Multi
Multi
Multi
HEC
Multi
Multi
Multi
THEM6
14
—
0
6
0
BIT
32
09
31
24
08
30
23
07
01
CP.THMRC
Cell Processor Transmit HEC Error Mask Control Register
(1,3,5,7)A6h
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-
THEM5
13
—
5Ch-66h
6Ch-6Fh
39h-3Fh
59h-5Ah
68h-6Ah
71h-7Fh
0
5
0
32h-37h
41h-42h
44h-50h
52h-53h
55h-56h
81h-85h
VALUE
5Bh
6Bh
38h
40h
43h
51h
54h
57h
58h
67h
70h
80h
86h
THEM4
12
—
0
0
4
341
ERROR
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
TYPE
Multi
Multi
HEC
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
HEC
Multi
THEM3
11
—
0
3
0
BIT
11
22
20
06
04
28
10
29
13
18
16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Table 12-48
THEM2
ACh-ADh
C8h-CDh
CFh-D5h
D7h-DFh
9Ch-A1h
A9h-AAh
B7h-C6h
A3h-A7h
B1h-B5h
E1h-FFh
90h-9Ah
87h-88h
VALUE
10
—
0
2
0
ABh
AEh
CEh
9Bh
A2h
A8h
AFh
B0h
C7h
D6h
E0h
89h
B6h
indicates the type of error
THEM1
—
9
0
1
0
ERROR
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
TYPE
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
Multi
THEM0
—
8
0
0
0
BIT
25
02
12
21
14
19
05
17
26
03
15
27
–
–
–
–
–
–
–
–
–
–
–
–
–