DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 316

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.12 DS3/E3 PLCP
12.12.1 Transmit Side PLCP
The transmit side uses seven registers.
12.12.1.1 Register Map
Table 12-43. Transmit Side PLCP Register Map
12.12.1.2 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 4 to 3: Transmit M2 and M1 Byte Control (TMC[1:0]) – These two bits control the source of the transmit M2
and M1 bytes.
Bits 2 to 1: Transmit F1 Byte Control (TF1C[1:0]) – These two bits control the source of the transmit F1 byte.
Note: If TMC[1:0] is 00 and TF1C[1:0] is 01, the F1 byte will be invalid. If TMC[1:0] is 01 and TF1C[1:0] is 01, both
M2 and F1 will carry the transmit HDLC data link. If TMC[1:0] is 10 and TF1C[1:0] is 01, both M1 and F1 will carry
the transmit HDLC data link. When F1 and M# both carry the transmit HDLC data link, the F1 byte and M# byte in
the same frame may or may not be equal.
Bit 0: Automatic REI Defeat (AREID) – When 0, the REI is automatically generated based upon the parity (BIP-8)
errors detected in the receive PLCP Frame Processor. When 1, the REI is inserted from the G1 register bits
TREI[3:0].
(1,3,5,7)5Ch
(1,3,5,7)5Ah
(1,3,5,7)5Eh
(1,3,5,7)50h
(1,3,5,7)52h
(1,3,5,7)54h
(1,3,5,7)56h
(1,3,5,7)58h
ADDRESS
00 = concatenated M1 and M2 (128 kHz) from transmit HDLC controller.
01 = M2 (64kHz) from transmit HDLC controller; M1 from M1 byte register (PLCP.TM12BR).
10 = M2 from M2 byte register; M1 (64 kHz) from transmit HDLC controller.
11 = M2 from M2 byte register; M1 from M1 byte register
00 = transmit Trail Trace controller.
01 = transmit HDLC controller.
10 = F1 byte register (PLCP.TFGBR).
11 = reserved
15
—
—
0
7
0
PLCP.TM12BR
PLCP.TZ12BR
PLCP.TZ34BR
PLCP.TZ56BR
PLCP.TFGBR
PLCP.TEIR
REGISTER
PLCP.TCR
—
14
—
—
0
6
0
PLCP.TCR
PLCP Transmit Control Register
(1,3,5,7)50h
PLCP Transmit Control Register
PLCP Transmit Error Insertion Register
PLCP Transmit F1 and G1 Byte Register
PLCP Transmit M1 and M2 Byte Register
PLCP Transmit Z1 and Z2 Byte Register
PLCP Transmit Z3 and Z4 Byte Register
PLCP Transmit Z5 and Z6 Byte Register
Unused
13
—
—
0
5
0
REGISTER DESCRIPTION
TMC1
12
—
0
0
4
316
TMC0
11
—
0
3
0
TF1C1
10
—
0
2
0
TF1C0
—
9
0
1
0
AREID
—
8
0
0
0