DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 363

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.14.4.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Receive Minimum Packet Size (RMNS[7:0]) – These eight bits indicate the minimum allowable
packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing. Note: In FCS-32 mode,
packets with six bytes are the minimum packet size allowed, in FCS-16 mode, packets with four bytes are the
minimum packet size allowed, and when FCS processing is disabled, packets with two bytes are the minimum
packet size allowed. Packets less than the minimum size will be aborted.
Bit 5: Receive FCS Processing Disable (RFPD) – When 0, FCS processing is performed (the packets have an
FCS appended). When 1, FCS processing is disabled (the packets do not have an FCS appended).
Bit 4: Receive FCS-16 Enable (RF16) – When 0, the error checking circuit uses a 32-bit FCS. When 1, the error
checking circuit uses a 16-bit FCS. This bit is ignored when FCS processing is disabled.
Bit 3: Receive FCS Extraction Disable (RFED) – When 0, the FCS bytes are discarded. When 1, the FCS bytes
are passed on. This bit is ignored when FCS processing is disabled.
Bit 2: Receive Descrambling Disable (RDD) – When 0, descrambling is performed. When 1, descrambling is
disabled.
Bit 1: Receive Bit Reordering Enable (RBRE) – When 0, bit reordering is disabled (The first bit received is stored
in the MSB of the receive FIFO byte). When 1, bit reordering is enabled (The first bit received is stored in the LSB
of the receive FIFO byte).
Bit 0: Receive Pass-Through Enable (RPTE) – When 0, pass-through mode is disabled and packet processing is
enabled. When 1, pass-through mode is enabled, and all packet-processing functions except descrambling and bit
reordering are disabled.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Maximum Packet Size (RMX[15:0]) – These 16 bits indicate the maximum allowable
packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing. Note: If the maximum packet
length is less than the minimum packet length, all packets will be aborted. When packet processing is disabled,
these 16 bits indicate the "packet" size the incoming data is to be broken into.
Reserved
RMNS7
RMX15
RMX7
15
15
0
7
0
0
7
0
Reserved
RMNS6
RMX14
RMX6
14
14
0
6
0
0
6
0
PP.RCR
Packet Processor Receive Control Register
(1,3,5,7)C0h
PP.RMPSC
Packet Processor Receive Maximum Packet Size Control Register
(1,3,5,7)C2h
RMNS5
RMX13
RMX5
RFPD
13
13
0
5
0
0
5
0
RMNS4
RMX12
RMX4
RF16
12
12
0
0
0
0
4
4
363
RMNS3
RMX11
RMX3
RFED
11
11
0
3
0
0
3
0
RMNS2
RMX10
RMX2
RDD
10
10
0
2
0
1
2
0
RMNS1
RBRE
RMX9
RMX1
9
0
1
0
9
1
1
0
RMNS0
RMX8
RMX0
RPTE
8
0
0
0
8
0
0
0