DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 28

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3 DS3/E3 Internal Fractional (Subrate) ATM/Packet Mode
DS3/E3 Internal Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the
fractional overhead internally controlled. Major functional blocks for the DS3/E3 Internal Fractional Mode are shown
in
The “-OHM” modes are not allowed in fractional framing modes since the user is not able to distinguish between
internal framing overhead and external framing overhead bit locations.
Table 6-3. DS3/E3 Internal Fractional (IFRAC) ATM/Packet Mode Configuration Registers
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-3. DS3/E3 Internal Fractional ATM/Packet Mode
TOHMOn/
Figure
RLCLKn
RNEGn/
ROHMIn
RPOSn/
TLCLKn
TPOSn/
TNEGn/
RLCVn/
RDATn
TDATn
RXNn
RXPn
TXPn
TXNn
MODE
6-3. Mapping configuration is programmable on per-port basis and is shown in
Clock Rate
Receive
DS3/E3
Transmit
DS3/E3
Adapter
LIU
LIU
FM[5:0]
0XX010
0XX010
0XX010
0XX010
0XX010
0XX010
Decoder
Encoder
HDB3
B3ZS/
B3ZS/
HDB3
TUA1
TAIS
SIM[1:0]
GL.CR1
IEEE P1149.1
00
01
10
11
10
11
JTAG Test
Access Port
FEAC
DS3 / E3
DS3 / E3
Receive
Framer
Transmit
Formatter
Buffer
Trace
Trail
PORT.CR2
HDLC
PMCPE
28
X
X
1
1
0
0
GEN
UA1
TX FRAC
RX FRAC
Rx Packet
Processor
Processor
RX BERT
Processor
Processor
TX BERT
Tx Packet
Rx Cell
Tx Cell
Microprocessor
Interface
Table
6-3.
FIFO
FIFO
Tx
Rx
n = port # (1-4)