DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 49

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TOHMOn
TNEGn /
RXNn
TXNn
RXPn
TXPn
PIN
TYPE
Oa
Oa
O
Ia
Ia
Transmit Negative AMI / Line OH Mask
TNEGn: When the port line is configured for B3ZS, HDB3 or AMI mode and the
framer is not configured for one of the “-OHM” modes (see
transmit line interface pins are enabled (PORT.CR2.TLEN), a high on this pin
indicates that a negative pulse should be transmitted on the line. The signal is
updated on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TLCLKn line clock output pins, but it can be referenced to
the TCLKOn, TCLKIn, RLCLKn or RCLKOn pins.
This output signal can be inverted.
o
o
o
TOHMOn: When the framer is configured for one of the “-OHM” modes (see
10-32) and the transmit line interface pins are enabled (PORT.CR2.TLEN), the
transmit overhead mask signal is output on this pin. This signal is a delayed version of
TOHMIn or ROHMIn when in local loopback (three clock period delay). This signal will
be high to indicate that the data on TDATn is not valid data and can be overwritten by
external logic to add an external frame signal. This signal will be low to indicate that
the data on TDATn is valid. The signal is updated on the positive clock edge of the
referenced clock pin if the clock pin signal is not inverted, otherwise it is updated on
the falling edge of the clock. The signal is typically referenced to the TLCLKn line
clock output pins, but it can be referenced to the TCLKOn, TCLKIn, RLCLKn or
RCLKOn pins.
This output signal can be inverted.
Transmit Positive Analog
TXPn: This pin and the TXNn pin form a differential AMI output which is coupled to
the outbound 75Ω coaxial cable through a 2:1 step-down transformer
This output is enabled when the TX LIU is enabled and the output is enabled to be
driven. When it is not enabled, it is in a high impedance state.
o
o
o
Transmit Negative Analog
TXNn: This pin and the TXPn pin form a differential AMI output which is coupled to
the outbound 75Ω coaxial cable through a 2:1 step-down transformer
This output is enabled when the TX LIU is enabled and the output is enabled to be
driven. When it is not enabled, it is in a high impedance state.
o
o
o
Receive Positive analog
RXPn: This pin and the RXNn pin form a differential AMI input which is coupled to the
outbound 75Ω coaxial cable through a 2:1 step-up transformer
is used when the RX LIU is enabled and is ignored when the LIU is disabled.
o
o
o
Receive Negative analog
RXNn: This pin and the RXPn pin form a differential AMI input which is coupled to the
outbound 75Ω coaxial cable through a 2:1 step-up transformer
is used when the LIU is enabled and is ignored when the LIU is disabled.
o
o
o
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
CC52: 52 Mbps +20ppm
49
FUNCTION
Table
(Figure
(Figure
10-32) and the
(Figure
(Figure
1-1). This input
1-1). This input
Table
1-1).
1-1).