DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 53

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TPOHENn /
TPOHCLKn
TFOHENIn
TPDENIn /
TCLKOn /
TGCLKn /
PIN
TYPE
O
I
PLCP framing overhead bits when TPOHENn is active. The TPOHSOFn signal marks
the start of the framing bit sequence. This signal is sampled at the same time as the
TPOHCLKn signal transitions high to low.
This signal can be inverted.
TFOHn: When the port framer is configured for one of the DS3 or E3 internal or
external fractional framing modes, and the port is enabled the internal fractional
framing modes, this pin can be used to source the fractional overhead data. The
signal is sampled on the positive clock edge of the referenced clock pin if the clock
pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. The
signal is typically referenced to the TCLKIn transmit clock input pins, but it can be
referenced to the TLCLKn, TCLKOn / TGCLKn, RCLKOn and RLCLKn clock pins
This signal can be inverted.
Transmit Payload Data Enable Input / PLCP Overhead Enable / Fractional OH Enable
Input. See
TPDENIn: When the port is configured for the Flexible fractional mode, this pin is
used to enable payload data from the cell/packet processor. There is a three-clock
delay between TPDENIn and TPDENOn. The signal is sampled on the positive clock
edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is
sampled on the falling edge of the clock. The signal is typically referenced to the
TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,
RCLKOn and RLCLKn clock pins
This signal can be inverted.
TPOHENn: When the port framer is configured for one of the DS3 or E3 PLCP
framing modes, and the port is enabled, this signal will be used the determine which
DS3 or E3 PLCP framing overhead bits to over-write with the signal on the TPOHn
pins. The TPOHSOFn signal marks the start of the framing bit sequence. This signal
is sampled at the same time as the TPOHCLKn signal transitions high to low.
This signal can be inverted.
TFOHENIn: When the port framer is configured for the DS3 or E3 External Fractional
framing, this pin is used to mark the fractional overhead data on the TFOHn pin. The
TSOFOn or TSOFIn pins can be used to select which DS3/E3 payload bits relative to
the start of the DS3/E3 frame to mark. The signal is sampled on the positive clock
edge of the referenced clock pin if the clock pin signal is not inverted, otherwise it is
sampled on the falling edge of the clock. The signal is typically referenced to the
TCLKIn transmit clock input pins, but it can be referenced to the TLCLKn, TCLKOn,
RCLKOn and RLCLKn clock pins
This signal can be inverted.
Transmit Clock Output / Gapped Clock / PLCP Overhead Clock. See
TCLKOn: When the port is configured external fractional modes and TCLKOn is
selected, or any other mode and the port pins are enabled and TCLKOn is selected,
this clock output is enabled. This clock is the same clock as the internal framer
transmit clock. This clock is typically used for the reference clock for the TOHMIn /
TSOFIn, TFOHn / TSERn, TFOHENIn and TSOFOn / TDENn / TFOHENOn signals
but can also be used as the reference for the TPOSn / TDATn and TNEGn /
TOHMOn signals.
This signal can be inverted.
o
o
o
TGCLKn: When the port is configured internal fractional mode or any simple DS3/E3
framed mode and the port pins are enabled and TGCLKn is selected, this gated
output clock is enabled. This gapped clock is the same clock as the internal framer
transmit clock and is gated by either TDENn or TFOHENOn depending on which
signal is active. This clock is typically used for the reference clock for the TFOHn /
TSERn signals.
This signal can be inverted.
TPOHCLKn: When the port framer is configured for one of the DS3 or E3 PLCP
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
CC52: 52 MHz +20 ppm
Table 10-22.
53
FUNCTION
Table 10-24.