DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 220

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Global Write Mode (GWRM) This bit enables the global write mode. When this bit is set, a write to the
register of any port will write to the same register in all the ports. Reading the registers of any port is not supported
and will read back undefined data.
Bit 14: INT pin mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
Bit 13: Direct Status Enable (DIREN) This bit selects between the direct status and polled status modes for
UTOPIA and POS-PHY.
Bits 11 and 10: System Interface Bus Width (SIW[1:0]) These bits configure the system bus width.
Bits 9 and 8: System Interface Mode (SIM[1:0]) These bits configure the system bus mode.
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used insert an error in all ports and error insertion logic
configured for global error insertion. An error(s) is inserted at the next opportunity when this bit transitions from low
to high. The GL.CR1.MEIMS bit must be clear for this bit to operate.
Bit 6: Transmit Manual Error Insert Select (MEIMS) This bit is used to select the source of the global manual
error insertion signal
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]) These bits select the global performance
monitor register update mode.
Bit 3: Global Performance Monitor Update Register (PMU) This bit is used to update all of the performance
monitor registers configured to use this bit. When this bit is toggled from low to high the performance registers
configured to use this signal will be updated with the latest count value from the counters, and the counters will be
reset. The bit should remain high until the performance register update status bit (GL.SR.PMS) goes high, then it
should be brought back low which clears the PMS status bit.
0 = Normal write mode
1 = Global write mode
0 = Pin is high impedance when not active
1 = Pin drives high when not active
0 = Polled status mode
1 = Direct status mode
00 = 8-bit
01 = 16-bit
1X = 32-bit
00 = UTOPIA L2
01 = UTOPIA L3
10 = POS-PHY L2
11 = POS-PHY L3 or SPI-3
0 = Global error insertion using TMEI bit
1 = Global error insertion using the GPIO6 pin
00 = Global PM update using the PMU bit
01 = Global PM update using the GPIO8 pin
1x = One second PM update using the internal one second counter
GWRM
TMEI
15
0
7
0
MEIMS
INTM
14
0
6
0
GL.CR1
Global Control Register 1
002h
DIREN
GPM1
13
0
5
0
GPM0
12
—
0
0
4
220
SIW1
PMU
11
0
3
0
LSBCRE
SIW0
10
0
2
0
RSTDP
SIM1
9
0
1
1
SIM0
RST
8
0
0
0