DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 169

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-34. C-Bit DS3 Frame Overhead Bit Definitions
X
the parity bits used for line error monitoring. M
frame alignment bits. C
has a value of one. C
value of one. C
End Block Error (FEBE) bits used for remote path error monitoring. C
data link (or HDLC) bits. C
have a value of one. The X-bit, P-bit, M-bit, C-bit, and F-bit positions are overhead bits, and the other bit positions
in the DS3 frame are payload bits.
10.10.5.2 Transmit C-bit DS3 Frame Generation
C-bit DS3 frame generation receives the incoming payload data stream, and overwrites the entire overhead bit
locations.
The multiframe alignment bits (M
respectively.
The sub-frame alignment bits (F
(1001) respectively.
The X-bits (X
programmable (automatic, 1, or 0). If the T3.TCR.ARDID is one then the T3.TCR.TRDI register bit controls this bit.
If the RDI is generated automatically (T3.TCR.ARDID=0), the X-bits are set to zero when one or more of the
indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are absent.
Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off) via the T3.TCR.PBGE register bit. The P-bits will be
generated if either P-bit generation is enabled or frame generation is enabled.
The bits C
C
C
C
C
C
C
M
1
21
31
41
51
61
71
and X
1
, C
, C
, C
, C
, C
, C
, M
X
P
22
32
42
52
62
72
BIT
2
F
C
C
C
1
1
, and M
, X
, P
, and C
, and C
, and C
, and C
, and C
, and C
XY
11
12
13
2
11
are the Remote Defect Indication (RDI) bits (also referred to as the far-end SEF/AIS bits). P
2
2
, C
1
1
12
31
and P
3
23
33
43
53
63
73
, C
, C
and X
21
32
Remote Defect Indication
(RDI)
Parity Bits
Multiframe Alignment Bits
Sub-frame Alignment Bits
Application Identification
Channel (AIC)
Reserved
Far-End Alarm and Control
(FEAC) signal
Unused
C-bit parity bits
Far-End Block Error (FEBE)
bits
Path Maintenance Data Link
(or HDLC) bits
Unused
Unused
, C
2
, and C
13
) are both overwritten with the calculated payload parity from the previous DS3 frame. The
11
2
22
is the Far-End Alarm and Control (FEAC) signal. C
) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
, C
is the Application Identification Channel (AIC). C
61
, C
23
33
DEFINITION
, C
are the C-bit parity bits used for path error monitoring. C
62
, and C
61
X1
, C
, F
1
, M
62
X2
, C
, F
2
63
, and M
63
are unused, and have a value of one. C
X3
, C
, and F
71
, C
1
, M
3
) are overwritten with the values zero, one, and zero (010)
72
2
, and C
X4
, and M
) are overwritten with the values one, zero, zero, and one
169
73
3
are all overwritten with a one.
are the multiframe alignment bits. F
51
, C
12
21
is reserved for future network use, and
52
, C
, and C
22
, and C
71
, C
53
72
41
are the path maintenance
23
, and C
, C
are unused, and have a
42
, and C
73
are unused, and
XY
43
are the sub-
1
are the Far-
and P
2
are