DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 147

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
Inter-frame padding inserts start flags, end flags and inter-frame fill between packets. There will be at least one flag
plus a programmable number of additional flags between packets. In octet aligned mode, the inter-frame fill is flags.
In bit synchronous mode, the inter-frame fill can be flags or all 1s followed by a start flag. If the inter-frame fill is all
'1's, the number of '1's between the end and start flags may not be an integer number of bytes, however, there will
be at least 15 consecutive '1's between the end and start flags. The bit synchronous mode inter-frame padding type
is programmable. If packet processing is disabled, inter-frame padding is not performed.
Packet abort insertion inserts a packet abort sequences as necessary. If a packet abort indication is detected, a
packet abort sequence is inserted and inter-frame padding is done until a packet start flag is detected. In bit
synchronous mode, the abort sequence is FFh. In octet aligned mode, the abort sequence is 7D7Eh. If packet
processing is disabled, packet abort insertion is not performed.
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The packet scrambler is a x
+ 1 self-synchronous scrambler that scrambles the entire packet data stream. Packet
scrambling is programmable.
Once all packet processing has been completed, in bit synchronous mode, the 8-bit parallel data stream is
multiplexed into a serial data stream and passed on. In octet aligned mode, the 8-bit parallel data stream is passed
on.
10.7.6.2 Receive Packet Processor
The Receive Packet Processor performs packet descrambling, packet delineation, inter-frame fill filtering, packet
abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering.
The data coming in can be either a serial data stream or an 8-bit parallel data stream, depending on the framing
mode (see
Table 10-32
for configuration information). The type of data stream received affects packet
descrambling, packet delineation, inter-frame fill filtering, packet abort detection, and destuffing, however, it does
not affect packet size checking, FCS error monitoring, FCS byte extraction, or bit reordering. Packet processing
can be disabled (clear-channel enable). Disabling packet processing disables packet delineation, inter-frame fill
filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, and FCS byte extraction.
Only packet descrambling and bit reordering are not disabled.
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The packet descrambler is a self-synchronous x
+ 1 descrambler that descrambles the entire packet data stream.
Packet descrambling is programmable. If packet processing is disabled in bit synchronous mode, the serial data
stream is demultiplexed in to an 8-bit data stream before being passed on.
If packet processing is disabled, a packet boundary is arbitrarily chosen, and the data is divided into "packets"
whose size is programmable (maximum packet size setting). These packets are then passed on to bit reordering
bypassing packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS
error monitoring, and FCS byte extraction.
Packet delineation determines the packet boundary by identifying a packet start or end flag. Each time slot is
checked for a flag sequence (7Eh). Once a flag is found, it is identified as a start or end flag, and the packet
boundary is set. If packet processing is disabled, packet delineation is not performed.
Inter-frame fill filtering removes the inter-frame fill between packets. When a packet end flag is detected, all data is
discarded until a packet start flag is detected. In bit synchronous mode, the inter-frame fill can be flags or all '1's.
When the interframe fill is all ‘1’s, the number of '1's between the start and end flags does not need to be an integer
number of bytes. In bit synchronous mode when inter-frame fill is flags, there may be only one flag between
packets, or the flags may have a shared zero (011111101111110). In octet aligned mode, the inter-frame fill can
only be flags, and there may be only one flag between packets. If packet processing is disabled, inter-frame fill
filtering is not performed.
Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if
an abort sequence is detected, the packet is marked with an abort indication, the aborted packet count is
incremented, and all subsequent data is discarded until a packet start flag is detected. In bit synchronous mode,
the abort sequence is seven consecutive ones. In octet aligned mode, the abort sequence is 7D7Eh. If packet
processing is disabled, packet abort detection is not performed.
Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. In bit
synchronous mode, bit destuffing is performed. Bit destuffing consists of discarding any '0' that directly follows five
contiguous '1's. In octet aligned mode, byte destuffing is performed. Byte destuffing consists of detecting an escape
sequence (7Dh), discarding it and exclusive ORing the next byte with 20h. In bit synchronous mode, after
destuffing is completed, the serial bit stream is demultiplexed into an 8-bit parallel data stream and passed on to
packet size checking. If there is less than eight bits in the last byte, an invalid packet flag is raised, the packet is
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