DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 311

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 8: Receive Unframed All 1’s (RUA1) – When 0, the receive frame processor is not in a receive unframed all
1’s (RUA1) condition. When 1, the receive frame processor is in an RUA1 condition.
Bit 0: Loss Of Signal (LOS) – When 0, the receive loss of signal (LOS) input (RLOS) is low. When 1, RLOS is
high.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 8: Receive Unframed All 1’s Latched (RUA1L) – This bit is set when the RUA1 bit changes state.
Bit 0: Loss Of Signal Change Latched (LOSL) – This bit is set when the LOS bit changes state.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 8: Receive Unframed All 1’s Interrupt Enable (RUA1IE) – This bit enables an interrupt if the RUA1L bit is set.
Bit 0: Loss Of Signal Interrupt Enable (LOSIE) – This bit enables an interrupt if the LOSL bit is set.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
15
15
15
0
7
0
0
7
0
0
7
0
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
14
14
14
0
6
0
0
6
0
0
6
0
CC.RSR1
Clear-Channel Receive Status Register 1
(1,3,5,7)24h
CC.RSRL1
Clear-Channel Receive Status Register Latched 1
(1,3,5,7)28h
CC.RSRIE1
Clear-Channel Receive Status Register Interrupt Enable 1
(1,3,5,7)2Ch
Reserved
Reserved
Reserved
Reserved
13
13
13
—
—
0
5
0
0
5
0
0
5
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
12
12
12
0
0
0
0
0
0
4
4
4
311
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
11
11
11
0
3
0
0
3
0
0
3
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10
10
10
0
2
0
0
2
0
0
2
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
9
0
1
0
9
0
1
0
9
0
1
0
RUA1IE
RUA1L
LOSIE
RUA1
LOSL
LOS
8
0
0
0
8
0
0
0
8
0
0
0