DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 256

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.7 HDLC
12.7.1 HDLC Transmit Side Register Map
The transmit side uses five registers.
Table 12-27. Transmit Side HDLC Register Map
12.7.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 12 to 8: Transmit HDLC Data Storage Available Level (TDAL[4:0]) – These five bits indicate the minimum
number of bytes ([TDAL*8]+1) that must be available for storage (do not contain data) in the Transmit FIFO for
HDLC data storage to be available. For example, a value of 21 (15h) results in HDLC data storage being available
(THDA = 1) when the Transmit FIFO has 169 (A9h) bytes or more available for storage, and HDLC data storage
not being available (THDA = 0) when the Transmit FIFO has 168 (A8h) bytes or less available for storage. Default
value (after reset) is 128 bytes minimum available.
Bit 6: Transmit Packet Start Disable (TPSD) – When 0, the Transmit Packet Processor will continue sending
packets after the current packet end. When 1, the Transmit Packet Processor will stop sending packets after the
current packet end.
Bit 5: Transmit FCS Error Insertion (TFEI) – When 0, the calculated FCS (inverted CRC-16) is appended to the
packet. When 1, the inverse of the calculated FCS (non-inverted CRC-16) is appended to the packet causing a
FCS error. This bit is ignored if transmit FCS processing is disabled (TFPD = 1).
Bit 4: Transmit Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag sequence (7Eh).
When 1, inter-frame fill is done with all ‘1’s.
Bit 3: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is the
LSB of the Transmit FIFO Data byte TFD[0]). When 1, bit reordering is enabled (The first bit transmitted is the MSB
of the Transmit FIFO Data byte TFD[7]).
Bit 2: Transmit Data Inversion Enable (TDIE) – When 0, the outgoing data is directly output from packet
processing. When 1, the outgoing data is inverted before being output from packet processing.
(0,2,4,6)ACh
(0,2,4,6)AAh
(0,2,4,6)AEh
(0,2,4,6)A0h
(0,2,4,6)A2h
(0,2,4,6)A4h
(0,2,4,6)A6h
(0,2,4,6)A8h
ADDRESS
15
—
—
0
7
0
HDLC.TSRIE
HDLC.TFDR
HDLC.TSRL
REGISTER
HDLC.TCR
HDLC.TSR
—
—
—
TPSD
14
—
0
6
0
HDLC Transmit Control Register
HDLC Transmit FIFO Data Register
HDLC Transmit Status Register
HDLC Transmit Status Register Latched
HDLC Transmit Status Register Interrupt Enable
Unused
Unused
Unused
HDLC.TCR
HDLC Transmit Control Register
(0,2,4,6)A0h
TFEI
13
—
0
5
0
REGISTER DESCRIPTION
TDAL4
TIFV
12
0
0
4
256
TDAL3
TBRE
11
1
3
0
TDAL2
TDIE
10
0
2
0
TDAL1
TFPD
9
0
1
0
TFRST
TDAL0
8
0
0
0