DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 61

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DS3181

Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3181

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3181+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3181N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
RDXA[4:2]
RSOX
REOP
PIN
TYPE
Oz
Oz
O
In UTOPIA L2 or UTOPIA L3 modes, RPXA goes high when the polled port has more
than a programmable number of ATM cells ready for transfer ("almost empty" level of
the associated FIFO). RPXA goes low when the polled port’s FIFO does not have a
complete ATM cell ready for transfer.
In POS-PHY L2 mode, RPXA goes high when the polled port’s FIFO contains more
data than the "almost empty" level or has an end of packet ready for transfer. RPXA
goes low when the port does not have an end of packet ready for transfer and is
"almost empty".
In UTOPIA L2 (reset default) or POS-PHY L2 modes, this signal is driven when one
of the ports is being polled, and is tri-stated when none of the ports is being polled or
when data path reset is active.
In UTOPIA L3 mode this signal is driven.
RSX: This signal is active in POS-PHY L3 modes and indicates the start of a data
transfer. This signal is updated on the rising edge of RSCLK.
RSX goes high immediately before the start of data transfer to indicate that the in-
band port address is present on RDATA. RSX goes high when the value of RDATA
is the address of the receive port from which data is to be transferred. When RSX
goes low, all subsequent transfers will be from the port specified by the in-band
address. When RSX is high, RVAL must be low.
This signal is always driven in POS-PHY L3 mode.
Receive Direct Cell/Packet Available [4:2]
RDXA[4:2]: This signal is used to indicate when the associated port can send data
to the ATM/Link layer device. This signal is updated on the rising edge of RSCLK.
In UTOPIA L2 or UTOPIA L3 modes, RDXA goes high when the associated port has
more than a programmable number of ATM cells ready for transfer ("almost empty"
level). RDXA goes low when the associated port does not have a complete ATM cell
ready for transfer.
In POS-PHY L2 mode, RDXA goes high when the associated port’s FIFO contains
more data than the "almost empty" level or has an end of packet ready for transfer.
RDXA goes low when the associated port’s FIFO does not have an end of packet
ready for transfer and is "almost empty".
In POS-PHY Level 3 (or SPI-3) mode or when polled status mode is selected, these
signals are held low.
Receive Start Of Cell/Packet (tri-state)
This signal is tri-state when global reset is applied.
RSOX: This signal is used to indicate the first transfer of a cell/packet. This signal is
updated on the rising edge of RSCLK.
In UTOPIA L2 or UTOPIA L3 modes, RSOX is used to indicate the first transfer of a
cell.
In POS-PHY L2 or POS-PHY L3 modes, RSOX is used to indicate the first transfer of
a packet.
In UTOPIA L2 (reset default) or POS-PHY L2 modes, this signal is driven when one
of the ports is selected for data transfer, and tri-stated when REN is deasserted,
none of the ports is selected or data path reset is active.
In UTOPIA L3 or POS-PHY L3 modes this signal is driven.
Receive End Of Packet (tri-state)
This signal is tri-state when global reset is applied.
REOP: In POS-PHY L2 or POS-PHY L3 modes, this signal is used to indicate the
last transfer of a packet. This signal is updated on the rising edge of RSCLK.
In UTOPIA L3 mode, this signal is held low.
In POS-PHY L2 mode, this signal is driven when one of the ports is selected for data
transfer, and tri-stated when REN is deasserted, none of the ports is selected or data
path reset is active.
In UTOPIA L2 (reset default) mode this signal is tri-stated.
In all UTOPIA L3 or POS-PHY L3 modes this signal is driven.
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