DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 92

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9
STEP 1: Check Device ID Code.
Before any testing can be done, the device ID code, which is stored in GL.IDR, should be checked against device
ID codes shown below to ensure that the correct device is being used.
Current device ID codes are:
STEP 2: Initialize the Device.
Before configuring for operation, make sure the device is in a known condition with all registers set to their default
value by initiating a Global Reset. (See Section 10.3) A Global Reset can be initiated via the RST pin or by the
Global Reset bit (GL.CR1.RST). A Port Reset is not necessary since the global reset includes a reset of all ports to
their default values.
STEP 3: Clear the Reset.
It is necessary to clear the RST bit to begin normal operation.
After clearing the RST bit, the device is configured for default mode.
Default mode:
STEP 4: Clear the Data Path Resets and the Port Power-Down bit.
The default value of the Data Path Resets is one, which keeps the internal logic in the reset status. The user needs
to clear the following bits:
STEP 5: Configure the CLAD.
STEP 6: Select the clock source for the transmitter.
STEP 7: Configure the Framing Mode and the Line Mode.
STEP 8: Disable Payload AIS (downstream AIS) and Line AIS
STEP 9: Initialize and configure the FIFOs.
INITIALIZATION AND CONFIGURATION
o
o
o
o
System Interface: UTOPIA Level 2, 8-bit databus
Framer: C-bit DS3
LIU: Disabled
GL.CR1.RSTDP = 0
PORT.CR1.RSTDP = 0
PORT.CR1.PD = 0
If using the LIU, configure the CLAD (the Clock Rate Adapter, which supplies the clock to the Receive LIU)
via the CLAD bits in
the
Note: The user must supply a DS3, E3, or STS-1 clock to the CLKA pin.
Loop Time (use the receive clock): Set PORT.CR3.LOOPT = 1
CLAD Source: Set PORT.CR3.CLADC = 0
TCLKI Source: Set PORT.CR3.CLADC = 1
If using the CLAD, properly configure the CLAD by setting the CLAD bits in
PORT.CR2.LM[2:0] = 011 -LIU on, JA in RX side-or another setting. See
PORT.CR2.FM[5:0] set to the correct framing mode. See
PORT.CR1.PAIS[2:0] = 111
PORT.CR1.LAIS[1:0] = 11
Reset the Transmit and Receive FIFO.
GL.CR2
DS3181 rev 1.0:
DS3182 rev 1.0:
DS3183 rev 1.0:
DS3184 rev 1.0:
FF.TCR.TFRST = 1.
register.
0048h
0049h
004Ah
004Bh
92
Table
10-32.
Table
GL.CR2.
10-33.