DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 99

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
10.2 Clocks
10.2.1 Line Clock Modes
The system loopback (SLB) function does not affect the line clocks in any way.
10.2.1.1 Loop Timing Enabled
When loop timing is enabled (PORT.CR3.LOOPT), the transmit clock source is the same as the receive clock
source. The TCLKIn pins are not used as a clock source. Because loop timing is enabled, the loopback functions
(LLB, PLB and DLB) do not cause the clock sources to switch when they are activated. The transmit and receive
signal pins can be timed to a single clock reference without concern about having the clock source change during
loopbacks.
10.2.1.1.1 LIU Enabled, Loop Timing Enabled
In this mode, the receive LIU sources the clock for both the receive and transmit logic. The RCLKOn, TCLKOn and
TLCLKn clock output pins will be the same. The transmit or receive line, payload and fractional signal pins can be
timed to any of these clock. The use of the RCLKOn pin as the timing source is suggested. If RCLKOn is used as
the timing source, be sure to set PORT.CR3.RFTS = 0 for output timing.
10.2.1.1.2 LIU Disabled, Loop Timing Enabled
In this mode, the RLCLKn pins are the source of the clock for both the receive and transmit logic. The RCLKOn,
TCLKOn and TLCLKn clock output pins will both be the same as the RLCLKn clock. The transmit or receive line,
payload and fractional signals can be timed to any of these clock pins. The use of the RLCLKn pin as the timing
source is suggested. If RLCLKn is used as the timing source, be sure to set PORT.CR3.RFTS = 1 for input timing.
10.2.1.2 Loop Timing Disabled
When loop timing is disabled, the transmit clock source can be different than the receive clock source. The
loopback functions, LLB, PLB and DLB, will cause the clock sources to switch when they are activated. Care must
be taken when selecting the clock reference for the transmit and receive signals.
The most versatile clocking option has the receive line interface signals timed to RLCLKn, the transmit line
interface signals timed to TLCLKn, the receive framer and fractional signals timed to RCLKOn, and the transmit
framer and fractional signals timed to TCLKOn. This clocking arrangement works in all modes.
When LLB is enabled, the clock on the TLCLKn pins will switch to the clock from the RLCLKn pins or RX LIU. It is
recommended that the transmit line interface signals be timed to the TLCLKn pins. If TLCLKn is used as the timing
source, be sure to set PORT.CR3.TLTS = 0 for output timing.
When PLB is enabled, the TCLKIn pin will not be used and the internal transmit clock is switched to the internal
receive clock. The clock on the TCLKOn pins will switch to the clock from the RLCLKn pins or RX LIU. The framer
or fractional input signals will be ignored while PLB is enabled. It is recommended that the transmit line interface
signals be timed to the TCLKOn pins.
When DLB is enabled, the internal receive clock is switched to the internal transmit clock which is sourced from the
TCLKIn pins or one of the CLAD clocks, and the clock on the RLCLKn pins or from the RX LIU will not be used.
The clock on the RCLKOn pins will switch to the clock on the TCLKIn pins or one of the CLAD clocks. The receive
line signals from the RX LIU or line interface pins will be ignored. It is recommended that the receive framer and
fractional pins be timed to the RCLKOn pins. If TCLKOn is used as the timing source, be sure to set
PORT.CR3.TFTS = 0 for output timing.
When both DLB and LLB are enabled, the TLCLKn clock pins are connected to either the RX LIU recovered clock
or the RLCLKn clock pins, and the RCLKOn clock pins will be connected to the TCLKIn clock pins or one of the
CLAD clocks. It is recommended that the transmit line signals be timed to the TLCLKn pins, the receive line
interface signals be timed to the RLCLKn pins, the receive framer and fractional signals be timed to the RCLKOn
pins, and the transmit framer and fractional signals be timed to the TCLKOn pins.
10.2.1.2.1 LIU Enabled - CLAD Timing Disabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and the TCLKIn pins source the clock for the
transmit logic.
99