DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 279

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.10.2 Receive DS3 Register Map
The receive DS3 uses 11 registers. Two registers are shared for C-Bit and M23 DS3 modes. The M23 DS3 mode
does not use the RFEBER or RCPECR count registers.
Table 12-34. Receive DS3 Framer Register Map
12.10.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 14: C-bit Overhead Masking Disable (COVHD) – When 0, the C-bit positions will be marked as overhead
(RDENn=0). When 1, the C-bit positions will be marked as data (RDENn=1). This bit is ignored in C-bit DS3 mode
or when the ROMD bit is set to one.
Bit 13: Multiframe Alignment OOF Disable (MAOD) – When 0, an OOF condition is declared whenever an
OOMF or SEF condition is declared. When 1, an OOF condition is declared only when an SEF condition is
declared.
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of a LOS, OOF, or AIS condition
will cause downstream AIS to be inserted. When 1, the presence of a LOS, OOF, or AIS condition will not cause
downstream AIS to be inserted.
Bit 10: Error Count Control (ECC) – When 0, framing errors, P-bit parity errors, C-bit parity errors, and far-end
block errors will not be counted if an OOF or AIS condition is present. P-bit parity errors, C-bit parity errors, and far-
end block errors will also not be counted during the DS3 frame in which an OOF condition is terminated, and the
next DS3 frame. When 1, framing errors, P-bit parity errors, C-bit parity errors, and far-end block errors will be
counted regardless of the presence of an OOF or AIS condition.
(1,3,5,7)2Ch
(1,3,5,7)3Ch
(1,3,5,7)2Ah
(1,3,5,7)2Eh
(1,3,5,7)3Ah
(1,3,5,7)3Eh
(1,3,5,7)20h
(1,3,5,7)22h
(1,3,5,7)24h
(1,3,5,7)26h
(1,3,5,7)28h
(1,3,5,7)30h
(1,3,5,7)32h
(1,3,5,7)34h
(1,3,5,7)36h
(1,3,5,7)38h
ADDRESS
Reserved
RAILE
15
0
7
0
T3.RCPECR
T3.RFBECR
REGISTER
T3.RSRIE1
T3.RSRIE2
T3.RFECR
T3.RPECR
T3.RSRL1
T3.RSRL2
T3.RSR1
T3.RSR2
T3.RCR
—
—
—
—
—
COVHD
RAILD
14
0
6
0
T3 Receive Control Register
Reserved
T3 Receive Status Register 1
T3 Receive Status Register 2
T3 Receive Status Register Latched 1
T3 Receive Status Register Latched 2
T3 Receive Status Register Interrupt Enable 1
T3 Receive Status Register Interrupt Enable 2
Reserved
Reserved
T3 Receive Framing Error Count Register
T3 Receive P-Bit Parity Error Count Register
T3 Receive Far-End Block Error Count Register
T3 Receive C-Bit Parity Error Count Register
Unused
Unused
T3.RCR
T3 Receive Control Register
(1,3,5,7)20h
RAIOD
MAOD
13
0
5
0
REGISTER DESCRIPTION
MDAISI
RAIAD
12
0
0
4
279
ROMD
AAISD
11
0
3
0
ECC
LIP1
10
0
2
0
FECC1
LIP0
9
0
1
0
FRSYNC
FECC0
8
0
0
0