DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 60

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RDATA[31:0]
RDXA[1] /
RPRTY
RPXA /
REN
RSX
PIN
TYPE
Oz
Oz
Oz
I
Receive Data [31:0] (tri-state)
This signal is tri-state when global reset is applied.
RDATA[31:0]: This 32-bit data bus is used to transfer cell/packet data to the
ATM/Link layer device. This bus is updated on the rising edge of RSCLK.
In 32-bit mode-
In 16-bit mode-
In 8-bit mode (reset default)-
In UTOPIA L3 or POS-PHY L3 modes, RDATA[31:0] are driven.
Receive Parity (tri-state)
RPRTY: This signal indicates the parity on the data bus when parity generation is
enabled. This option programmable. RPRTY is held low if parity generation is
disabled. This signal is updated on the rising edge of RSCLK.
In UTOPIA L2 (reset default) or POS-PHY L2 modes, this signal is driven when one
of the ports is selected for data transfer, and tri-stated when REN is deasserted,
none of the ports is selected or data path reset is active.
In UTOPIA L3 or POS-PHY L3 modes this signal is driven.
Receive Enable (active low)
REN: This signal is used by the ATM/Link device to control the transfer of cell/packet
data on the RDATA bus. If REN is high, no transfer occurs. If REN is low, a transfer
occurs. This signal can be sampled on the rising edge of RSCLK.
Receive Direct Cell/Packet Available [1] / Polled Cell/Packet Available / Start of
Transfer (tri-state)
This signal is tri-state when global reset is applied.
RDXA[1]: This signal is active in UTOPIA L2, Utopia L3 or POS-PHY L2 modes
when direct status mode is selected. It is used to indicate when port 1 can send data
to the ATM/Link layer device. This signal is updated on the rising edge of RSCLK.
In UTOPIA L2 or UTOPIA L3 modes, RDXA goes high when the port 1 FIFO has
more than a programmable number of ATM cells ready for transfer ("almost empty"
level). RDXA goes low when the associated port does not have a complete ATM cell
ready for transfer.
In POS-PHY L2 mode, RDXA goes high when the port 1 FIFO contains more data
than the "almost empty" level or has an end of packet ready for transfer. RDXA goes
low when the associated port does not have an end of packet ready for transfer and
is "almost empty".
RPXA: (Reset default) This signal is active in UTOPIA L2, UTOPIA L3 or POS-PHY
L2 modes when polled status mode is selected. It is used to indicate when the polled
port, as selected by RADR[4:0], can send data to the ATM/Link layer device. This
signal is updated on the rising edge of RSCLK.
RDATA[31] is the MSB and RDATA[0] is the LSB.
In UTOPIA L2 or POS-PHY L2 modes, RDATA[31:0] are driven when one of
the ports is selected for data transfer, and tri-stated when REN is deasserted,
none of the ports is selected or data path reset is active.
In UTOPIA L3 or POS-PHY L3 modes RDATA[31:0] are driven.
RDATA[15] is the MSB, RDATA[0] is the LSB, and RDATA[31:16] are not
used.
In UTOPIA L2 or POS-PHY L2 modes, RDATA[15:0] are driven when one of
the ports is selected for data transfer, and tri-stated when REN is deasserted,
none of the ports is selected or data path reset is active. RDATA[31:16] are
tri-stated.
In UTOPIA L3 or POS-PHY L3 modes, RDATA[31:0] are driven.
RDATA[7] is the MSB, RDATA[0] is the LSB, and RDATA[31:8] are not used.
In UTOPIA L2 (reset default) or POS-PHY L2 modes, RDATA[7:0] are driven
when one of the ports is selected for data transfer, and tri-stated when REN
is deasserted, none of the ports is selected or data path reset is applied.
RDATA[31:8] are tri-stated.
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FUNCTION