DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 55

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RFOHENIn
RPDENIn /
TPDENOn
RPDATn
TPDATn
RSERn /
RPOHn
PIN
TYPE
O
O
O
I
I
Transmit Payload Data Enable Output. See
TPDENOn: When the port framer is enabled for the Flexible fractional mode and the
port pins are enabled, this signal marks which bits on the TPDATn pin are valid
payload data bits. It is high during the same clock cycle the TPDATn payload data bit
is valid. The signal is updated on the positive clock edge of the referenced clock pin if
the clock pin signal is not inverted, otherwise it is updated on the falling edge of the
clock. The signal is typically referenced to the TCLKIn transmit clock input pin, but it
can be referenced to the TLCLKn, TCLKOn, RCLKOn or RLCLKn clock pin.
This signal can be inverted.
Transmit Payload Data. See
TPDATn: When the port framer is enabled for the Flexible fractional mode and the
port pins are enabled, this signal is the payload bits from the cell/packet processor.
The data is valid if the TPDENOn signal is high during the same clock cycle. The
signal is updated on the positive clock edge of the referenced clock pin if the clock pin
signal is not inverted, otherwise it is updated on the falling edge of the clock. The
signal is typically referenced to the TCLKIn transmit clock input pin, but it can be
referenced to the TLCLKn, TCLKOn, RCLKOn or RLCLKn clock pin.
This signal can be inverted.
Receive Payload Data Enable Input / Fractional Overhead Enable Input
See
RPDENIn: When the port is configured for the flexible fractional mode, this pin is used
to enable payload data for the cell/packet processor. The data on RPDATn is used
when this signal is high. The signal is sampled on the positive clock edge of the
referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled on
the falling edge of the clock. The signal is typically referenced to the RCLKOn receive
clock output pins, but it can be referenced to the RLCLKn clock input pin.
This signal can be inverted.
RFOHENIn: When the port framer is configured for the external fractional framing
mode, this pin is used to mark the receive bits to use for fractional overhead data. The
signal on the RSOFOn pin can be used to select which DS3/E3 payload bits relative
to the start of the DS3/E3 frame to
the RSERn pin that should be treated as fractional overhead in the DS3/E3 payload.
RFOHENIn needs to go high or low three clock periods after the data bit on RSERn is
present to mark that bit as payload or fractional overhead. The signal is sampled on
the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is sampled on the falling edge of the clock. The signal is typically
referenced to the RCLKOn receive clock output pins, but it can be referenced to the
RLCLKn clock input pin.
This signal can be inverted.
Receive Payload Data. See
RPDATn: When the port framer is enabled for the Flexible fractional mode and the
port pins are enabled, this signal is the payload bits for the cell/packet processor. The
data is used if the RPDENOn signal is high during the same clock cycle. The signal is
sampled on the positive clock edge of the referenced clock pin if the clock pin signal
is not inverted, otherwise it is sampled on the falling edge of the clock. The signal is
typically referenced to the RCLKOn receive clock output pins, but it can be referenced
to the RLCLKn clock input pin.
This signal can be inverted.
Receive Serial Data / PLCP Overhead. See
RSERn: When the port framer is configured for the external fractional mode, internal
fractional mode, or flexible fractional mode, and the port pins are enabled, this pin
outputs the receive data signal from the LIU or receive line pins. The signal is updated
on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the RCLKOn receive clock output pin, but it can be referenced to the
RGCLKn and RLCLKn clock pins.
This signal can be inverted
Table 10-28.
Table
Table
55
10-29.
mark.
10-26.
FUNCTION
The signal needs to go high for each bit on
Table 10-26.
Table 10-27.