DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 193

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Immediately after a reset (or datapath reset) or a LOS condition, a BPV will not be declared when the first
valid one (RPOS high and RNEG low, or RPOS low and RNEG high) is received. Bipolar to unipolar conversion
converts the AMI bipolar data into a unipolar signal by ORing together the RXP and RXN signals.
10.15 BERT
10.15.1 General Description
The BERT is a software-programmable test-pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudo-random
patterns with a generation polynomial of the form x
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern.
devices.
Figure 10-54. BERT Block Diagram
10.15.2 Features
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•
•
•
•
10.15.3 Configuration and Monitoring
Set PORT.CR1.BENA = 1 to enable the BERT. The BERT must be enabled before the pattern is loaded for the
pattern load operation to take affect.
The following tables show how to configure the on-board BERT to send and receive common patterns.
Programmable PRBS pattern – The Pseudo Random Bit Sequence (PRBS) polynomial (x
are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2
Programmable repetitive pattern – The repetitive pattern length and pattern are programmable (the length n
= 1 to 32 and pattern = 0 to 2
24-bit error count and 32-bit bit count registers
Programmable bit error insertion – Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10
Pattern synchronization at a 10
random Bit Error Rate (BER) of 10
Clock Rate
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Decoder
n
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
is programmable (n = 1 to 7).
TUA1
TAIS
n
- 1).
-3
-3
IEEE P1149.1
.
BER – Pattern synchronization will be achieved even in the presence of a
JTAG Test
Access Port
FEAC
DS3 / E3
Framer
DS3 / E3
Transmit
Receive
Figure 10-54
Formatter
Buffer
Trace
Trail
HDLC
n
+ x
y
193
GEN
UA1
+ 1, where n and y can take on values from 1 to 32 and to
shows the location of the BERT Block within the DS318x
TX FRAC/
PLCP
RX FRAC/
PLCP
n
- 1).
Rx Packet
Processor
Processor
Processor
Processor
RX BERT
Tx Packet
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
n
+ x
FIFO
FIFO
Tx
Rx
y
+ 1) and seed