DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 247

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DS3181

Manufacturer Part Number
DS3181
Description
Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3181

Product
Framer
Number Of Transceivers
1
Data Rate
44.736 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
280 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TEBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3181+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3181N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 3: Performance Monitoring Update Status (PMS) – This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS
will be forced low when the LPMU bit (PMUM = 0) or the global or port PMU bit (PMUM=1) goes low.
Bit 1: Bit Error Count (BEC) – When 0, the bit error count is zero. When 1, the bit error count is one or more. This
bit is cleared when the user updates the BERT counters via the PMU bit (BERT.CR).
Bit 0: Out Of Synchronization (OOS) – When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 3: Performance Monitoring Update Status Latched (PMSL) – This bit is set when the PMS bit transitions
from 0 to 1.
Bit 2: Bit Error Latched (BEL) – This bit is set when a bit error is detected.
Bit 1: Bit Error Count Latched (BECL) – This bit is set when the BEC bit transitions from 0 to 1.
Bit 0: Out Of Synchronization Latched (OOSL) – This bit is set when the OOS bit changes state.
15
15
7
7
14
14
6
6
BERT.SR
BERT Status Register
(0,2,4,6)6Ch
BERT.SRL
BERT Status Register Latched
(0,2,4,6)6Eh
13
13
5
5
12
12
4
4
247
PMSL
PMS
11
11
3
3
BEL
10
10
2
2
BECL
BEC
9
1
9
1
OOSL
OOS
8
0
8
0

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