DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 359

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Transmit Errored Packet Insertion Finished (TEPF) – This bit is set when the number of errored packets
indicated by the TPEN[7:0] bits in the PP.TEPC register have been transmitted. This bit is cleared when errored
packet insertion is disabled, or a new errored packet insertion process is initiated.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Transmit Errored Packet Insertion Finished Latched (TEPFL) – This bit is set when the TEPF bit in the
PP.TSR register transitions from zero to one.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Transmit Errored Packet Insertion Finished Interrupt Enable (TEPFIE) – This bit enables an interrupt if
the TEPFL bit in the PP.TSRL register is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
15
15
15
—
—
—
—
—
—
7
7
0
7
0
14
14
14
—
—
—
—
—
—
6
6
0
6
0
PP.TSR
Packet Processor Transmit Status Register
(1,3,5,7)AEh
PP.TSRL
Packet Processor Transmit Status Register Latched
(1,3,5,7)B0h
PP.TSRIE
Packet Processor Transmit Status Register Interrupt Enable
(1,3,5,7)B2h
13
13
13
—
—
—
—
—
—
5
5
0
5
0
12
—
12
—
12
—
—
—
—
0
0
4
4
4
359
11
11
11
—
—
—
—
—
—
3
3
0
3
0
10
10
10
—
—
—
—
—
—
2
2
0
2
0
—
—
—
—
—
—
9
1
9
1
9
0
1
0
TEPFIE
TEPFL
TEPF
—
—
—
8
0
8
0
8
0
0
0