DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 93

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STEP 10: Configure the System Bus
STEP 11: Configure the Cell or Packet Processor
STEP 12: Enable each port (for non-LIU modes)
Table 9-1. Configuration of Global Register Settings
Note: This table assumes a DS3 clock input on the CLKA pin.
UTOPIA L2
UTOPIA L3
POS-PHY L2
POS-PHY L3 or SPI-3
8-Bit System Bus
16-Bit System Bus
32-Bit System Bus
Table 9-2. Configuration of Port Register Settings
Note: The Line Mode has been configured with the LIU enabled and the JA in the receive path (LM[2:0] = 011) for all modes except OHM mode.
Only Port 1 registers have been displayed.
DS3 C-Bit
DS3 C-Bit PLCP
DS3 M23
DS3 M23 PLCP
E3.751
E3.751 PLCP
E3.823
OHM Mode (DS3/E3/Clear
Channel)
Clear the FIFO Reset bits.
Set the FIFO Transmit Level Control Register and the FIFO Transmit Port Address Control Register.
Set the FIFO Receive Level Control Register and the FIFO Receive Port Address Control Register.
The Port Address needs to be configured to match the master controller address for each port.
Configure for bus size and for interface type. See
Optionally, set the System Interface Transmit Control Register, System Interface Receive Control Register
#1 and #2 to fine tune for the specific application.
(User may leave registers at default value.)
For cell mode, the default is to send the cell across the system interface without the HEC. Also, default
mode scrambles the cell data to the line.
To attach the HEC to the cell, set SI.TCR.THECT = 1 and SI.RCR.RHECT = 1.
PORT.CR2.TLEN = 1
MODE
MODE
FF.RCR.RFRST = 1.
FF.TCR.TFRST = 0.
FF.RCR.RFRST = 0.
0000 XX00 0000 0000
0000 XX01 0000 0000
0000 XX10 0000 0000
0000 XX11 0000 0000
0000 00XX 0000 0000
0000 01XX 0000 0000
0000 10XX 0000 0000
PORT.CR1
0x7C00
0x7C00
0x7C00
0x7C00
0x7C00
0x7C00
0x7C00
0x7C00
0x040
GL.CR1
0x002
1100 0XXX 00XX XXXX
0000 0011 0000 000X
0000 0011 0000 010X
0000 0011 0000 100X
0000 0011 0000 110X
0000 0011 0001 000X
0000 0011 0001 010X
0000 0011 0001 100X
PORT.CR2
0x042
93
GL.CR20x00
Table
0x0204
0x0204
0x0204
0x0204
0x0204
0x0204
0x0204
4
9-1.
PORT.CR3
GL.GIOCR
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00A
0x044
PORT.CR4
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x046