DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 26

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
The major operational modes are determined by the FM[5:0] framer mode bits and a few other control bits. Unused
features are powered down and the data paths are held in reset. The configuration registers of the unused features
can be written to and read from. The function of some IO pins change in different operational modes. The line
interface operational mode is determined by the LM[2:0] bits.
6.1 DS3/E3 ATM/Packet Mode
DS3/E3 ATM/Packet mode is a normal mode of operation for the DS318x device, which maps/demaps ATM cells
or packet data into a DS3 or E3 data stream via the selected mapping mode. Major functional blocks for the
DS3/E3 ATM/Packet mode are shown in
is shown in
Table 6-1. DS3/E3 ATM/Packet Mode Configuration Registers
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-1. DS3/E3 ATM/Packet Mode
TOHMOn/
RLCLKn
RNEGn/
ROHMIn
RPOSn/
TLCLKn
TPOSn/
TNEGn/
RLCVn/
RDATn
TDATn
RXNn
RXPn
TXPn
TXNn
MAJOR OPERATIONAL MODES
MODE
Clock Rate
Receive
Table
DS3/E3
Transmit
DS3/E3
Adapter
LIU
LIU
6-1.
FM[5:0]
0XX000
0XX000
0XX000
0XX000
0XX000
0XX000
Decoder
Encoder
HDB3
B3ZS/
B3ZS/
HDB3
TUA1
TAIS
SIM[1:0]
GL.CR1
Figure
IEEE P1149.1
00
01
10
11
10
11
JTAG Test
Access Port
FEAC
DS3 / E3
DS3 / E3
Receive
Framer
Transmit
Formatter
Buffer
6-1. Mapping configuration is programmable on per-port basis and
Trace
Trail
PORT.CR2
HDLC
PMCPE
26
X
X
1
1
0
0
GEN
UA1
Rx Packet
Processor
Processor
RX BERT
Processor
Processor
TX BERT
Tx Packet
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
FIFO
Tx
Rx
n = port # (1-4)