DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 267

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.8.2 FEAC Receive Side Register Map
The receive side uses five registers.
Table 12-30. FEAC Receive Side Register Map
12.8.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Receive FEAC Reset (RFR) –When 0, the Receive FEAC Processor and Receive FEAC FIFO will resume
normal operations. When 1, the Receive FEAC controller is reset. The FEAC FIFO is emptied, any transfer in
progress is halted, and all incoming data is discarded.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 3: Receive FEAC FIFO Empty (RFFE) – When 0, the Receive FIFO contains at least one code. When 1, the
Receive FIFO is empty.
Bit 1: Receive FEAC Codeword Detect (RFCD) – When 0, the Receive FEAC Processor is not currently receiving
a FEAC codeword. When 1, the Receive FEAC Processor is currently receiving a FEAC codeword.
Bit 0: Receive FEAC Idle (RFI) – When 0, the Receive FEAC processor is not receiving a FEAC Idle signal (all
ones). When 1, the Receive FEAC processor is receiving a FEAC Idle signal.
(0,2,4,6)DAh
(0,2,4,6)DCh
(0,2,4,6)DEh
(0,2,4,6)D0h
(0,2,4,6)D2h
(0,2,4,6)D4h
(0,2,4,6)D6h
(0,2,4,6)D8h
ADDRESS
15
15
—
—
—
—
0
7
0
7
FEAC.RSRIE
FEAC.RFDR
FEAC.RSRL
REGISTER
FEAC.RCR
FEAC.RSR
—
—
—
14
14
—
—
—
—
0
6
0
6
FEAC Receive Control Register
Unused
FEAC Receive Status Register
FEAC Receive Status Register Latched
FEAC Receive Status Register Interrupt Enable
Unused
FEAC Receive FIFO Data Register
Unused
FEAC.RCR
FEAC Receive Control Register
(0,2,4,6)D0h
FEAC.RSR
FEAC Receive Status Register
(0,2,4,6)D4h
13
13
—
—
—
—
0
5
0
5
REGISTER DESCRIPTION
12
12
—
—
—
—
0
0
4
4
267
RFFE
11
11
—
—
—
1
3
0
3
10
10
—
—
—
—
0
2
0
2
RFCD
—
—
—
9
0
1
0
9
1
RFR
RFI
—
—
8
0
0
0
8
0